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CD74AC175NSRG4 PDF预览

CD74AC175NSRG4

更新时间： 2024-01-14 16:18:25
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件
页数 文件大小 规格书
13页 763K
描述
IC AC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, GREEN, PLASTIC, SOP-16, FF/Latch

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CD74AC175NSRG4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP16,.3
针数：16Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.62
系列：ACJESD-30 代码：R-PDSO-G16
长度：10.2 mm负载电容（CL）：50 pF
逻辑集成电路类型：D FLIP-FLOP最大频率@ Nom-Sup：71000000 Hz
最大I（ol）：0.012 A位数：4
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3/5 V传播延迟（tpd）：153 ns
认证状态：Not Qualified座面最大高度：2 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.5 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：5.3 mm最小 fmax：100 MHz
Base Number Matches：1

CD74AC175NSRG4 数据手册

 浏览型号CD74AC175NSRG4的Datasheet PDF文件第2页浏览型号CD74AC175NSRG4的Datasheet PDF文件第3页浏览型号CD74AC175NSRG4的Datasheet PDF文件第4页浏览型号CD74AC175NSRG4的Datasheet PDF文件第5页浏览型号CD74AC175NSRG4的Datasheet PDF文件第6页浏览型号CD74AC175NSRG4的Datasheet PDF文件第7页 
CD74AC175  
QUADRUPLE D-TYPE FLIP-FLOP  
WITH CLEAR  
SCHS347 – APRIL 2003  
M PACKAGE  
(TOP VIEW)  
AC Types Feature 1.5-V to 5.5-V Operation  
and Balanced Noise Immunity at 30% of the  
Supply Voltage  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CLR  
1Q  
1Q  
1D  
2D  
2Q  
2Q  
GND  
V
CC  
Buffered Inputs  
4Q  
4Q  
4D  
3D  
3Q  
3Q  
CLK  
Contains Four Flip-Flops With Double-Rail  
Outputs  
Speed of Bipolar F, AS, and S, With  
Significantly Reduced Power Consumption  
Balanced Propagation Delays  
±24-mA Output Drive Current  
– Fanout to 15 F Devices  
SCR-Latchup-Resistant CMOS Process and  
Circuit Design  
Exceeds 2-kV ESD Protection Per  
MIL-STD-883, Method 3015  
Applications Include:  
– Buffer/Storage Registers  
– Shift Registers  
– Pattern Generators  
description/ordering information  
This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74AC175 features  
complementary outputs from each flip-flop.  
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the  
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not  
directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low  
level, the D input has no effect at the output.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
Tube  
CD74AC175M  
–55°C to 125°C  
SOIC – M  
AC175M  
Tape and reel CD74AC175M96  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUTS  
CLR  
L
CLK  
D
X
H
L
Q
L
Q
H
L
X
↑
H
H
L
H
↑
H
H
L
X
Q
Q
0
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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