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CD74AC20M PDF预览

CD74AC20M

更新时间: 2024-02-06 05:28:10
品牌 Logo 应用领域
德州仪器 - TI 栅极逻辑集成电路光电二极管
页数 文件大小 规格书
5页 32K
描述
Dual 4-Input NAND Gate

CD74AC20M 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SOP, SOP14,.25Reach Compliance Code:unknown
风险等级:5.81Is Samacsys:N
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.012 A端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:3.3/5 V
Prop。Delay @ Nom-Sup:17.1 ns认证状态:Not Qualified
施密特触发器:NO子类别:Gates
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

CD74AC20M 数据手册

 浏览型号CD74AC20M的Datasheet PDF文件第2页浏览型号CD74AC20M的Datasheet PDF文件第3页浏览型号CD74AC20M的Datasheet PDF文件第4页浏览型号CD74AC20M的Datasheet PDF文件第5页 
CD74AC20,  
CD54/74ACT20  
Data sheet acquired from Harris Semiconductor  
SCHS229A  
Dual 4-Input NAND Gate  
September 1998 - Revised May 2000  
Features  
Description  
• Typical Propagation Delay  
o
The CD74AC20 and ’ACT20 are dual 4-input NAND gates that  
utilize Advanced CMOS Logic technology.  
- 6ns at V  
= 5V, T = 25 C, C = 50pF  
A L  
CC  
• Exceeds 2kV ESD Protection MIL-STD-883, Method  
3015  
Ordering Information  
PART  
NUMBER  
TEMP.  
• SCR-Latchup-Resistant CMOS Process and Circuit  
Design  
o
RANGE ( C)  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
PACKAGE  
14 Ld PDIP  
CD74AC20E  
• Speed of Bipolar FAST™/AS/S with Significantly  
Reduced Power Consumption  
[ /Title  
(CD74  
AC20,  
CD74  
ACT20  
)
CD74AC20M  
CD54ACT20F3A  
CD74ACT20E  
CD74ACT20M  
NOTES:  
14 Ld SOIC  
14 Ld CERDIP  
14 Ld PDIP  
14 Ld SOIC  
• Balanced Propagation Delays  
• AC Types Feature 1.5V to 5.5V Operation and  
Balanced Noise Immunity at 30% of the Supply  
±24mA Output Drive Current  
- Fanout to 15 FAST™ ICs  
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
/Sub-  
ject  
- Drives 50Transmission Lines  
2. Wafer and die for this part number is available which meets all elec-  
trical specifications. Please contact your local TI sales office or cus-  
tomer service for ordering information.  
(Dual  
4-Input  
NAND  
Gate)  
/Autho  
r ()  
/Key-  
words  
(Har-  
ris  
Semi-  
con-  
ductor,  
Advan  
ced  
CMOS  
,Harris  
Semi-  
con-  
ductor,  
Advan  
ced  
TTL)  
/Cre-  
ator ()  
Pinout  
Functional Diagram  
CD54ACT20  
(CERDIP)  
CD74AC20, CD74ACT20  
(PDIP, SOIC)  
1
1A  
2
1B  
6
1Y  
4
TOP VIEW  
1C  
5
1D  
1A  
1B  
1
2
3
4
5
6
7
14 V  
CC  
9
2A  
13 2D  
12 2C  
11 NC  
10 2B  
10  
2B  
8
NC  
1C  
2Y  
12  
13  
2C  
GND = 7  
V
= 14  
CC  
NC = 3, 11  
2D  
1D  
1Y  
9
8
2A  
2Y  
TRUTH TABLE  
GND  
INPUTS  
nB nC  
OUTPUTS  
nA  
L
nD  
X
nY  
H
H
H
H
L
X
L
X
X
L
X
X
X
X
X
H
X
X
X
H
L
H
H
X = Don’t Care  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
FAST™ is a Trademark of Fairchild Semiconductor.  
1
Copyright © 2000, Texas Instruments Incorporated  

CD74AC20M 替代型号

型号 品牌 替代类型 描述 数据表
CD74AC20M96G4 TI

完全替代

2 通道、4 输入、1.5V 至 5.5V 与非门 | D | 14 | -55 to 1
CD74AC20M96 TI

类似代替

2 通道、4 输入、1.5V 至 5.5V 与非门 | D | 14 | -55 to 1

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