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CD74AC08EE4 PDF预览

CD74AC08EE4

更新时间: 2024-11-20 20:08:23
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管逻辑集成电路
页数 文件大小 规格书
14页 873K
描述
AND Gate, AC Series, 4-Func, 2-Input, CMOS, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14

CD74AC08EE4 技术参数

生命周期:Contact Manufacturer包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.72系列:AC
JESD-30 代码:R-PDIP-T14长度:19.305 mm
逻辑集成电路类型:AND GATE功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
传播延迟(tpd):109 ns座面最大高度:5.08 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.5 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

CD74AC08EE4 数据手册

 浏览型号CD74AC08EE4的Datasheet PDF文件第2页浏览型号CD74AC08EE4的Datasheet PDF文件第3页浏览型号CD74AC08EE4的Datasheet PDF文件第4页浏览型号CD74AC08EE4的Datasheet PDF文件第5页浏览型号CD74AC08EE4的Datasheet PDF文件第6页浏览型号CD74AC08EE4的Datasheet PDF文件第7页 
CD54AC08, CD74AC08  
QUADRUPLE 2-INPUT POSITIVE-AND GATES  
SCHS307C – JANUARY 2001 – REVISED JUNE 2002  
CD54AC08 . . . F PACKAGE  
CD74AC08 . . . E OR M PACKAGE  
(TOP VIEW)  
AC Types Feature 1.5-V to 5.5-V Operation  
and Balanced Noise Immunity at 30% of the  
Supply Voltage  
Speed of Bipolar F, AS, and S, With  
Significantly Reduced Power Consumption  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
4B  
4A  
4Y  
Balanced Propagation Delays  
Buffered Inputs  
1Y  
2A  
2B  
10 3B  
±24-mA Output Drive Current  
– Fanout to 15 F Devices  
9
8
2Y  
3A  
3Y  
GND  
SCR-Latchup-Resistant CMOS Process and  
Circuit Design  
Exceeds 2-kV ESD Protection Per  
MIL-STD-883, Method 3015  
description  
The ’AC08 devices are quadruple 2-input positive-AND gates. These devices perform the Boolean function  
A B or Y B in positive logic.  
Y
A
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – E  
Tube  
Tube  
CD74AC08E  
CD74AC08E  
CD74AC08M  
–55°C to 125°C  
SOIC – M  
AC08M  
Tape and reel  
Tube  
CD74AC08M96  
CD54AC08F3A  
CDIP – F  
CD54AC08F3A  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB  
design guidelines are available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
H
X
L
H
L
H
L
L
X
logic diagram, each gate (positive logic)  
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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