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CD74AC109E PDF预览

CD74AC109E

更新时间： 2024-09-15 05:09:03
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
12页 346K
描述
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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中文翻译

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CD74AC109E 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：6 weeks风险等级：0.82
Is Samacsys：N系列：AC
JESD-30 代码：R-PDIP-T16JESD-609代码：e4
长度：19.3 mm负载电容（CL）：50 pF
逻辑集成电路类型：J-KBAR FLIP-FLOP最大频率@ Nom-Sup：71000000 Hz
最大I（ol）：0.024 A位数：2
功能数量：2端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
包装方法：TUBE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3/5 V最大电源电流（ICC）：0.04 mA
Prop。Delay @ Nom-Sup：11.1 ns传播延迟（tpd）：129 ns
认证状态：Not Qualified施密特触发器：No
座面最大高度：5.08 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：1.5 V
标称供电电压 (Vsup)：3.3 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：6.35 mm最小 fmax：100 MHz
Base Number Matches：1

CD74AC109E 数据手册

 浏览型号CD74AC109E的Datasheet PDF文件第2页浏览型号CD74AC109E的Datasheet PDF文件第3页浏览型号CD74AC109E的Datasheet PDF文件第4页浏览型号CD74AC109E的Datasheet PDF文件第5页浏览型号CD74AC109E的Datasheet PDF文件第6页浏览型号CD74AC109E的Datasheet PDF文件第7页 
CD54AC109, CD74AC109  
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCHS326 – JANUARY 2003  
CD54AC109 . . . F PACKAGE  
CD74AC109 . . . E OR M PACKAGE  
(TOP VIEW)  
AC Types Feature 1.5-V to 5.5-V Operation  
and Balanced Noise Immunity at 30% of the  
Supply Voltage  
Speed of Bipolar F, AS, and S, With  
Significantly Reduced Power Consumption  
1CLR  
1J  
V
CC  
2CLR  
2J  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
1K  
Balanced Propagation Delays  
1CLK  
1PRE  
1Q  
2K  
±24-mA Output Drive Current  
– Fanout to 15 F Devices  
2CLK  
11 2PRE  
SCR-Latchup-Resistant CMOS Process and  
Circuit Design  
10  
9
1Q  
2Q  
2Q  
GND  
Exceeds 2-kV ESD Protection Per  
MIL-STD-883, Method 3015  
description/ordering information  
The ’AC109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset  
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE  
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to  
the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and  
isnotdirectlyrelatedtotherisetimeoftheclockpulse. Followingthehold-timeinterval, dataattheJandKinputs  
can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle  
flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
PDIP – E  
SOIC – M  
CDIP – F  
Tube  
CD74AC109E  
CD74AC109E  
AC109M  
–55°C to 125°C  
Tape and reel CD74AC109M96  
Tube CD54AC109F3A  
CD54AC109F3A  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

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CD74AC109E 替代型号

型号 品牌 替代类型 描述 数据表
CD54ACT109F3A TI

完全替代

 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
CD54AC109F3A TI

完全替代

 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

与CD74AC109E相关器件

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CD74AC109EE4 TI

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 		DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
CD74AC109EN ETC

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 		Logic IC
CD74AC109EX GE

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 		J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output,
CD74AC109EX ROCHESTER

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 		J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output,
CD74AC109F ETC

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 		Logic IC
CD74AC109M TI

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 		AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PL
CD74AC109M GE

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 		J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output,
CD74AC109M ROCHESTER

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 		J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output,
CD74AC109M96 TI

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 		DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
CD74AC109M96 ROCHESTER

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 		J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output,

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