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CD54HCT40105F3A PDF预览

CD54HCT40105F3A

更新时间： 2024-11-26 22:03:11
品牌 Logo 应用领域
德州仪器 - TI 存储内存集成电路先进先出芯片时钟
页数 文件大小 规格书
19页 317K
描述
High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register

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CD54HCT40105F3A 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP16,.3针数：16
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.87
最长访问时间：2250 ns最大时钟频率 (fCLK)：10 MHz
周期时间：100 nsJESD-30 代码：R-GDIP-T16
长度：19.56 mm内存密度：64 bit
内存集成电路类型：OTHER FIFO内存宽度：4
功能数量：1端子数量：16
字数：16 words字数代码：16
工作模式：SYNCHRONOUS最高工作温度：125 °C
最低工作温度：-55 °C组织：16X4
可输出：YES封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
座面最大高度：5.08 mm子类别：FIFOs
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

CD54HCT40105F3A 数据手册

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CD54HC40105, CD74HC40105,  
CD54HCT40105, CD74HCT40105  
Data sheet acquired from Harris Semiconductor  
SCHS222C  
High-Speed CMOS Logic  
4-Bit x 16-Word FIFO Register  
February 1998 - Revised October 2003  
Features  
Description  
• Independent Asynchronous Inputs and Outputs  
• Expandable in Either Direction  
• Reset Capability  
The ’HC40105 and ’HCT40105 are high-speed silicon-gate  
CMOS devices that are compatible, except for “shift-out”  
circuitry, with the CD40105B. They are low-power first-in-out  
(FIFO) “elastic” storage registers that can store 16 four-bit  
words. The 40105 is capable of handling input and output  
data at different shifting rates. This feature makes it  
particularly useful as a buffer between asynchronous  
systems.  
[ /Title  
(CD74  
HC401  
05,  
CD74  
HCT40  
105)  
/Sub-  
ject  
(High  
Speed  
CMOS  
• Status Indicators on Inputs and Outputs  
• Three-State Outputs  
• Shift-Out Independent of Three-State Control  
• Fanout (Over Temperature Range)  
Each work position in the register is clocked by a control flip-  
flop, which stores a marker bit. A “1” signifies that the posi-  
tion’s data is filled and a “0” denotes a vacancy in that posi-  
tion. The control flip-flop detects the state of the preceding  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
flip-flop and communicates its own status to the succeeding  
o
• Wide Operating Temperature Range . . . -55 C to 125 C flip-flop. When a control flip-flop is in the “0” state and sees a  
“1” in the preceeding flip-flop, it generates a clock pulse that  
transfers data from the preceding four data latches into its  
• Balanced Propagation Delay and Transition Times  
own four data latches and resets the preceding flip-flop to  
“0”. The first and last control flip-flops have buffered outputs.  
Since all empty locations “bubble” automatically to the input  
end, and all valid data ripple through to the output end, the  
status of the first control flip-flop (DATA-IN READY) indicates  
if the FIFO is full, and the status of the last flip-flop (DATA-  
OUT READY) indicates if the FIFO contains data. As the  
earliest data are removed from the bottom of the data stack  
(the output end), all data entered later will automatically  
propagate (ripple) toward the output.  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
Ordering Information  
IL  
IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
o
PART NUMBER  
CD54HC40105F3A  
CD54HCT40105F3A  
CD74HC40105E  
TEMP. RANGE ( C)  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
Applications  
• Bit-Rate Smoothing  
• CPU/Terminal Buffering  
• Data Communications  
• Peripheral Buffering  
• Line Printer Input Buffers  
• Auto-Dialers  
CD74HC40105M  
CD74HC40105MT  
CD74HC40105M96  
CD74HCT40105E  
CD74HCT40105M  
CD74HCT40105MT  
CD74HCT40105M96  
• CRT Buffer Memories  
• Radar Data Acquisition  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel  
of 250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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