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CD54HCT259F3A

更新时间: 2024-11-05 22:17:43
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德州仪器 - TI 锁存器
页数 文件大小 规格书
12页 271K
描述
High-Speed CMOS Logic 8-Bit Addressable Latch

CD54HCT259F3A 数据手册

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CD54HC259, CD74HC259,  
CD54HCT259, CD74HCT259  
Data sheet acquired from Harris Semiconductor  
SCHS173C  
High-Speed CMOS Logic  
8-Bit Addressable Latch  
November 1997 - Revised October 2003  
Features  
Description  
• Buffered Inputs and Outputs  
• Four Operating Modes  
• Typical Propagation Delay of 15ns at V  
The ’HC259 and ’HCT259 Addressable Latch features the  
low-power consumption associated with CMOS circuitry and  
has speeds comparable to low-power Schottky.  
[ /Title  
(CD74  
HC259  
,
CD74  
HCT25  
9)  
= 5V,  
CC  
This latches three active modes and one reset mode. When  
both the Latch Enable (LE) and Master Reset (MR) inputs are  
low (8-line Demultiplexer mode) the output of the addressed  
latch follows the Data input and all other outputs are forced  
low. When both MR and LE are high (Memory Mode), all  
outputs are isolated from the Data input, i.e., all latches hold  
o
C = 15pF, T = 25 C  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C the last data presented before the LE transition from low to  
high. A condition of LE low and MR high (Addressable Latch  
mode) allows the addressed latch’s output to follow the data  
input; all other latches are unaffected. The Reset mode (all  
outputs low) results when LE is high and MR is low.  
/Sub-  
ject  
• Balanced Propagation Delay and Transition Times  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
(High  
Speed  
CMOS  
Logic  
8-Bit  
Addres  
sable  
Latch)  
• HC Types  
Ordering Information  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
CC  
TEMP. RANGE  
o
IL  
IH  
PART NUMBER  
CD54HC259F3A  
CD54HCT259F3A  
CD74HC259E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
at V  
= 5V  
CC  
• HCT Types  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
CD74HC259M  
CD74HC259MT  
CD74HC259M96  
CD74HCT259E  
CD74HCT259M  
CD74HCT259MT  
CD74HCT259M96  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel  
of 250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

CD54HCT259F3A 替代型号

型号 品牌 替代类型 描述 数据表
CD74HCT259M TI

完全替代

High Speed CMOS Logic 8-Bit Addressable Latch
CD74HCT259E TI

完全替代

High Speed CMOS Logic 8-Bit Addressable Latch
CD74HCT259M96 TI

完全替代

High-Speed CMOS Logic 8-Bit Addressable Latch

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