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CD54HCT166

更新时间： 2024-11-04 05:18:03
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德州仪器 - TI 移位寄存器
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High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register

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CD54HC166, CD74HC166,  
CD54HCT166, CD74HCT166  
Data sheet acquired from Harris Semiconductor  
SCHS157C  
High-Speed CMOS Logic  
8-Bit Parallel-In/Serial-Out Shift Register  
February 1998 - Revised October 2003  
Features  
Description  
• Buffered Inputs  
The ’HC166 and ’HCT166 8-bit shift register is fabricated  
with silicon gate CMOS technology. It possesses the low  
power consumption of standard CMOS integrated circuits,  
and can operate at speeds comparable to the equivalent low  
power Schottky device.  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
[ /Title  
(CD74  
HC166  
,
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
The ’HCT166 is functionally and pin compatible with the  
standard ’LS166.  
CD74  
HCT16  
6)  
/Sub-  
ject  
(High  
Speed  
CMOS  
Logic  
8-Bit  
Paral-  
lel-  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
The 166 is an 8-bit shift register that has fully synchronous  
serial or parallel data entry selected by an active LOW Parallel  
Enable (PE) input. When the PE is LOW one setup time before  
the LOW-to-HIGH clock transition, parallel data is entered into  
the register. When PE is HIGH, data is entered into the internal  
bit position Q0 from Serial Data Input (DS), and the remaining  
bits are shifted one place to the right (Q0 → Q1 → Q2, etc.)  
with each positive-going clock transition. For expansion of the  
register in parallel to serial converters, the Q7 output is con-  
nected to the DS input of the succeeding stage.  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
• HCT Types  
= 5V  
CC  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL  
IH  
The clock input is a gated OR structure which allows one  
input to be used as an active LOW Clock Enable (CE) input.  
The pin assignment for the CP and CE inputs is arbitrary and  
can be reversed for layout convenience. The LOW-to-HIGH  
transition of CE input should only take place while the CP is  
HIGH for predictable operation.  
Pinout  
CD54HC166, CD54HCT166  
(CERDIP)  
CD74HC166, CD74HCT166  
(PDIP, SOIC)  
In/Seri  
A LOW on the Master Reset (MR) input overrides all other  
inputs and clears the register asynchronously, forcing all bit  
positions to a LOW state.  
TOP VIEW  
DS  
D0  
1
2
3
4
5
6
7
8
16 V  
CC  
15 PE  
14 D7  
13 Q7  
12 D6  
11 D5  
10 D4  
Ordering Information  
D1  
o
D2  
PART NUMBER  
CD54HC166F3A  
CD54HCT166F3A  
CD74HC166E  
TEMP. RANGE ( C)  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
D3  
CE  
CP  
9
MR  
GND  
CD74HC166M  
CD74HC166MT  
CD74HC166M96  
CD74HCT166E  
CD74HCT166M  
CD74HCT166MT  
CD74HCT166M96  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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