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CD54HCT173

更新时间： 2024-11-03 22:03:11
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德州仪器 - TI 触发器
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17页 372K
描述
High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State

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CD54HC173, CD74HC173,  
CD54HCT173, CD74HCT173  
Data sheet acquired from Harris Semiconductor  
SCHS158E  
High-Speed CMOS Logic  
Quad D-Type Flip-Flop, Three-State  
February 1998 - Revised October 2003  
Features  
Description  
The ’HC173 and ’HCT173 high speed three-state quad D-  
type flip-flops are fabricated with silicon gate CMOS technol-  
ogy. They possess the low power consumption of standard  
CMOS Integrated circuits, and can operate at speeds com-  
• Three-State Buffered Outputs  
• Gated Input and Output Enables  
• Fanout (Over Temperature Range)  
[ /Title  
(CD74H  
C173,  
CD74H  
CT173)  
/Subject  
(High  
Speed  
CMOS  
Logic  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads parable to the equivalent low power Schottky devices. The  
buffered outputs can drive 15 LSTTL loads. The large output  
drive capability and three-state feature make these parts ide-  
ally suited for interfacing with bus lines in bus oriented sys-  
tems.  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
The four D-type flip-flops operate synchronously from a com-  
mon clock. The outputs are in the three-state mode when  
either of the two output disable pins are at the logic “1” level.  
The input ENABLES allow the flip-flops to remain in their  
present states without having to disrupt the clock If either of  
the 2 input ENABLES are taken to a logic “1” level, the Q  
outputs are fed back to the inputs, forcing the flip-flops to  
remain in the same state. Reset is enabled by taking the  
MASTER RESET (MR) input to a logic “1” level. The data  
outputs change state on the positive going edge of the clock.  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
CC  
IL  
IH  
at V  
= 5V  
CC  
Quad D-  
Type  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
l
OL OH  
The ’HCT173 logic family is functionally, as well as pin com-  
patible with the standard LS logic family.  
Ordering Information  
Pinout  
CD54HC173, CD54HCT173  
(CERDIP)  
CD74HC173  
(PDIP, SOIC, SOP, TSSOP)  
CD74HCT173  
TEMP. RANGE  
o
PART NUMBER  
CD54HC173F3A  
CD54HCT173F3A  
CD74HC173E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
(PDIP, SOIC)  
TOP VIEW  
OE  
1
2
3
4
5
6
7
8
16 V  
CC  
CD74HC173M  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOP  
15 MR  
14 D0  
13 D1  
12 D2  
11 D3  
10 E2  
OE2  
CD74HC173MT  
CD74HC173M96  
CD74HC173NSR  
CD74HC173PW  
CD74HC173PWR  
CD74HC173PWT  
CD74HCT173E  
CD74HCT173M  
CD74HCT173MT  
CD74HCT173M96  
Q
Q
Q
Q
0
1
2
3
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
CP  
9
E1  
GND  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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CD54HCT173F3A TI

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CD54HCT173F3A RENESAS

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