Datasheet > CD54HC40103_08

CD54HC40103_08

更新时间： 2024-11-27 05:09:03

品牌	Logo	应用领域
德州仪器 - TI		计数器
页数	文件大小	规格书
16页	454K
描述
High-Speed CMOS Logic 8-Stage Synchronous Down Counters

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CD54HC40103_08 数据手册

CD54HC40103, CD74HC40103,

CD74HCT40103

Data sheet acquired from Harris Semiconductor

SCHS221D

High-Speed CMOS Logic

8-Stage Synchronous Down Counters

November 1997 - Revised October 2003

Features

Description

• Synchronous or Asynchronous Preset

• Cascadable in Synchronous or Ripple Mode

The ’HC40103 and CD74HCT40103 are manufactured with

high speed silicon gate technology and consist of an 8-stage

synchronous down counter with a single output which is

active when the internal count is zero. The 40103 contains a

single 8-bit binary counter. Each has control inputs for

enabling or disabling the clock, for clearing the counter to its

maximum count, and for presetting the counter either

[ /Title

(CD74H

C40103,

CD74H

CT4010

/Sub-

ject

(High

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55 C to 125 C synchronously or asynchronously. All control inputs and the

TC output are active-low logic.

• Balanced Propagation Delay and Transition Times

In normal operation, the counter is decremented by one

• Signiﬁcant Power Reduction Compared to LSTTL

count on each positive transition of the CLOCK (CP).

Logic ICs

Counting is inhibited when the TE input is high. The TC

output goes low when the count reaches zero if the TE input

is low, and remains low for one full clock period.

• HC Types

Speed

CMOS

Logic 8-

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

When the PE input is low, data at the P0-P7 inputs are

clocked into the counter on the next positive clock transition

regardless of the state of the TE input. When the PL input is

low, data at the P0-P7 inputs are asynchronously forced into

the counter regardless of the state of the PE, TE, or CLOCK

inputs. Input P0-P7 represent a single 8-bit binary word for

the 40103. When the MR input is low, the counter is

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

asynchronously cleared to its maximum count of 255

regardless of the state of any other input. The precedence

relationship between control inputs is indicated in the truth

table.

Ordering Information

TEMP. RANGE

If all control inputs except TE are high at the time of zero

count, the counters will jump to the maximum count, giving a

PART NUMBER

CD54HC40103F3A

CD74HC40103E

( C)

PACKAGE

-55 to 125

16 Ld CERDIP

16 Ld PDIP

16 Ld SOIC

16 Ld PDIP

16 Ld SOIC

counting sequence of 100 or 256 clock pulses long.

16 10

The 40103 may be cascaded using the TE input and the TC

output, in either a synchronous or ripple mode. These

circuits possess the low power consumption usually

associated with CMOS circuitry, yet have speeds

comparable to low power Schottky TTL circuits and can drive

up to 10 LSTTL loads.

CD74HC40103M

CD74HC40103MT

CD74HC40103M96

CD74HCT40103E

CD74HCT40103M

CD74HCT40103MT

CD74HCT40103M96

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel

of 250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7...16

中文翻译

下载PDF

与CD54HC40103_08相关器件

型号	品牌	获取价格	描述	数据表
CD54HC40103E	ETC	获取价格	Logic IC
CD54HC40103EN	ETC	获取价格	Logic IC
CD54HC40103F	TI	获取价格	High-Speed CMOS Logic 8-Stage Synchronous Down Counters
CD54HC40103F	RENESAS	获取价格	IC,COUNTER,DOWN,8-BIT BINARY,HC-CMOS,DIP,16PIN,CERAMIC
CD54HC40103F/3	RENESAS	获取价格	HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT DOWN BINARY COUNTER, CDIP16
CD54HC40103F/3A	RENESAS	获取价格	IC HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT DOWN BINARY COUNTER, CDIP16, Counter
CD54HC40103F3A	TI	获取价格	High-Speed CMOS Logic 8-Stage Synchronous Down Counters
CD54HC40103F3A	RENESAS	获取价格	IC,COUNTER,DOWN,8-BIT BINARY,HC-CMOS,DIP,16PIN,CERAMIC
CD54HC40103H/3	RENESAS	获取价格	HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT DOWN BINARY COUNTER, UUC16
CD54HC40103H/3A	RENESAS	获取价格	HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT DOWN BINARY COUNTER, UUC16

与CD54HC40103_08相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

46
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

35
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

64
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

61

产品中心

服务支持

精选活动

关于我们

帮助中心

CD54HC40103_08

CD54HC40103_08 数据手册

与CD54HC40103_08相关器件

与CD54HC40103_08相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CD54HC40103_08

CD54HC40103_08 数据手册

与CD54HC40103_08相关器件

与CD54HC40103_08相关文章

您还可以找

您在本页遇到什么问题？