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CD54HC160F3A PDF预览

CD54HC160F3A

更新时间： 2024-11-25 04:35:11
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德州仪器 - TI 计数器触发器逻辑集成电路
页数 文件大小 规格书
14页 249K
描述
BCD SYNCHRONOUS DECADE COUNTERS

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中文翻译

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CD54HC160F3A 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP16,.3针数：16
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.76计数方向：UP
系列：HC/UHJESD-30 代码：R-GDIP-T16
长度：19.56 mm负载电容（CL）：50 pF
负载/预设输入：YES逻辑集成电路类型：DECADE COUNTER
最大频率@ Nom-Sup：20000000 Hz最大I（ol）：0.004 A
工作模式：SYNCHRONOUS位数：4
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2/6 V传播延迟（tpd）：280 ns
认证状态：Not Qualified筛选级别：MIL-STD-883
座面最大高度：5.08 mm子类别：Counters
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：4.5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：7.62 mm
最小 fmax：24 MHzBase Number Matches：1

CD54HC160F3A 数据手册

 浏览型号CD54HC160F3A的Datasheet PDF文件第2页浏览型号CD54HC160F3A的Datasheet PDF文件第3页浏览型号CD54HC160F3A的Datasheet PDF文件第4页浏览型号CD54HC160F3A的Datasheet PDF文件第5页浏览型号CD54HC160F3A的Datasheet PDF文件第6页浏览型号CD54HC160F3A的Datasheet PDF文件第7页 
CD54HC160, CD54HC162  
BCD SYNCHRONOUS DECADE COUNTERS  
SCHS301 – JUNE 2000  
CD54HC160, CD54HC162 . . . F PACKAGE  
(TOP VIEW)  
Synchronous Counting and Loading  
Two Count-Enable Inputs for n-Bit  
Cascading  
CLR  
CLK  
A
V
CC  
RCO  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Asynchronous Reset (CD54HC160)  
Synchronous Reset (CD54HC162)  
Q
A
B
Q
B
Look-Ahead Carry for High-Speed Counting  
C
Q
C
Operating Range 2-V to 6-V V  
CC  
D
Q
D
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
ENP  
GND  
ENT  
LOAD  
Packaged in Ceramic (F) DIPs  
description  
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed  
counting designs. The CD54HC160 and CD54HC162 are BCD decade counters. Synchronous operation is  
provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other  
when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation  
eliminates the output counting spikes that are normally associated with synchronous (ripple-clock) counters.  
A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.  
These counters are fully programmable; that is, they can be preset to any number between 0 and 9. As  
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs  
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.  
The clear function for the CD54HC160 is asynchronous. A low level at the clear (CLR) input sets all four of the  
flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.  
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without  
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).  
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a  
high-level pulse while the count is maximum (9 with Q high). This high-level overflow ripple-carry pulse can  
A
be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level  
of CLK.  
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that  
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of  
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the  
stable setup and hold times.  
The CD54HC160 and CD54HC162 are supplied in 16-lead hermetic dual-in-line ceramic packages (F suffix),  
and are characterized for operation over the full military temperature range of –55°C to 125°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

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与CD54HC160F3A相关器件

型号 品牌 获取价格 描述 数据表
CD54HC160H RENESAS

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 		CD54HC160H
CD54HC160H/3 RENESAS

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 		HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, UUC16
CD54HC160H/3A RENESAS

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 		Decade Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, C
CD54HC160M ETC

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 		Logic IC
CD54HC161 TI

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 		High-Speed CMOS Logic Presettable Counters
CD54HC161E ETC

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 		Logic IC
CD54HC161EN ETC

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 		Logic IC
CD54HC161F TI

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 		High-Speed CMOS Logic Presettable Counters
CD54HC161F/3 RENESAS

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 		HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16
CD54HC161F3A TI

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 		High-Speed CMOS Logic Presettable Counters

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