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CD54HC162 PDF预览

CD54HC162

更新时间: 2024-11-01 05:09:03
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德州仪器 - TI 计数器
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14页 249K
描述
BCD SYNCHRONOUS DECADE COUNTERS

CD54HC162 数据手册

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CD54HC160, CD54HC162  
BCD SYNCHRONOUS DECADE COUNTERS  
SCHS301 – JUNE 2000  
CD54HC160, CD54HC162 . . . F PACKAGE  
(TOP VIEW)  
Synchronous Counting and Loading  
Two Count-Enable Inputs for n-Bit  
Cascading  
CLR  
CLK  
A
V
CC  
RCO  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Asynchronous Reset (CD54HC160)  
Synchronous Reset (CD54HC162)  
Q
A
B
Q
B
Look-Ahead Carry for High-Speed Counting  
C
Q
C
Operating Range 2-V to 6-V V  
CC  
D
Q
D
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
ENP  
GND  
ENT  
LOAD  
Packaged in Ceramic (F) DIPs  
description  
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed  
counting designs. The CD54HC160 and CD54HC162 are BCD decade counters. Synchronous operation is  
provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other  
when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation  
eliminates the output counting spikes that are normally associated with synchronous (ripple-clock) counters.  
A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.  
These counters are fully programmable; that is, they can be preset to any number between 0 and 9. As  
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs  
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.  
The clear function for the CD54HC160 is asynchronous. A low level at the clear (CLR) input sets all four of the  
flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.  
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without  
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).  
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a  
high-level pulse while the count is maximum (9 with Q high). This high-level overflow ripple-carry pulse can  
A
be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level  
of CLK.  
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that  
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of  
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the  
stable setup and hold times.  
The CD54HC160 and CD54HC162 are supplied in 16-lead hermetic dual-in-line ceramic packages (F suffix),  
and are characterized for operation over the full military temperature range of –55°C to 125°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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