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CD54HC161F

更新时间： 2024-11-24 21:57:59
品牌 Logo 应用领域
德州仪器 - TI 计数器逻辑集成电路
页数 文件大小 规格书
16页 285K
描述
High-Speed CMOS Logic Presettable Counters

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CD54HC161F 技术参数

生命周期：Active零件包装代码：DIP
包装说明：DIP, DIP16,.3针数：16
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.13
其他特性：TCO OUTPUT计数方向：UP
系列：HC/UHJESD-30 代码：R-GDIP-T16
长度：19.56 mm负载电容（CL）：50 pF
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：20000000 Hz最大I（ol）：0.0052 A
工作模式：SYNCHRONOUS位数：4
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE包装方法：TUBE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2/6 V
最大电源电流（ICC）：0.08 mAProp。Delay @ Nom-Sup：39 ns
传播延迟（tpd）：280 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Counters
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：4.5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：6.92 mm
最小 fmax：24 MHzBase Number Matches：1

CD54HC161F 数据手册

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CD54/74HC161, CD54/74HCT161,  
CD54/74HC163, CD54/74HCT163  
The CD54HCT161 is obsolete  
and no longer is supplied.  
Data sheet acquired from Harris Semiconductor  
SCHS154D  
High-Speed CMOS Logic  
Presettable Counters  
February 1998 - Revised October 2003  
Two count enables, PE and TE, in each counter are  
provided for n-bit cascading. In all counters reset action  
occurs regardless of the level of the SPE, PE and TE inputs  
(and the clock input, CP, in the ’HC161 and ’HCT161  
types).  
Features  
• ’HC161, ’HCT161 4-Bit Binary Counter,  
Asynchronous Reset  
[ /Title  
(CD74  
HC161  
,
CD74  
HCT16  
1,  
CD74  
HC163  
,
CD74  
HCT16  
3)  
• ’HC163, ’HCT163 4-Bit Binary Counter,  
Synchronous Reset  
If a decade counter is preset to an illegal state or assumes  
an illegal state when power is applied, it will return to the  
normal sequence in one count as shown in state diagram.  
• Synchronous Counting and Loading  
• Two Count Enable Inputs for n-Bit Cascading  
• Look-Ahead Carry for High-Speed Counting  
The look-ahead carry feature simplifies serial cascading of  
the counters. Both count enable inputs (PE and TE) must  
be high to count. The TE input is gated with the Q outputs  
of all four stages so that at the maximum count the terminal  
count (TC) output goes high for one clock period. This TC  
pulse is used to enable the next cascaded stage.  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
TEMP. RANGE  
o
• HC Types  
PART NUMBER  
CD54HC161F3A  
CD54HC163F3A  
CD54HCT163F3A  
CD74HC161E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
/Sub-  
ject  
- 2V to 6V Operation  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
(High  
Speed  
CMOS  
Logic  
Preset-  
table  
Counte  
rs)  
/Autho  
r ()  
/Key-  
words  
(High  
Speed  
CMOS  
Logic  
Preset-  
table  
Counte  
rs,  
High  
Speed  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
CD74HC161M  
IL  
IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
CD74HC161MT  
CD74HC161M96  
CD74HC163E  
Description  
The ’HC161, ’HCT161, ’HC163, and ’HCT163 are  
presettable synchronous counters that feature look-ahead  
carry logic for use in high-speed counting applications. The  
’HC161 and ’HCT161 are asynchronous reset decade and  
binary counters, respectively; the ’HC163 and ’HCT163  
devices are decade and binary counters, respectively, that  
are reset synchronously with the clock. Counting and  
parallel presetting are both accomplished synchronously  
with the negative-to-positive transition of the clock.  
CD74HC163M  
CD74HC163MT  
CD74HC163M96  
CD74HCT161E  
CD74HCT161M  
CD74HCT161MT  
CD74HCT161M96  
CD74HCT163E  
CD74HCT163M  
CD74HCT163MT  
CD74HCT163M96  
A low level on the synchronous parallel enable input, SPE,  
disables counting operation and allows data at the P0 to P3  
inputs to be loaded into the counter (provided that the  
setup and hold requirements for SPE are met).  
All counters are reset with a low level on the Master Reset  
input, MR. In the ’HC163 and ’HCT163 counters  
(synchronous reset types), the requirements for setup and  
hold time with respect to the clock must be met.  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
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CD54HC161F 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC161M96 TI

完全替代

 High-Speed CMOS Logic Presettable Counters
CD74HC161M TI

完全替代

 High Speed CMOS Logic Presettable Counters
CD74HC161E TI

完全替代

 High Speed CMOS Logic Presettable Counters

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