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CD54HC138_07

更新时间： 2024-11-01 05:09:03
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德州仪器 - TI 解码器解复用器
页数 文件大小 规格书
18页 408K
描述
High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting

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CD54HC138_07 数据手册

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CD54/74HC138, CD54/74HCT138,  
CD54/74HC238, CD54/74HCT238  
Data sheet acquired from Harris Semiconductor  
SCHS147I  
High-Speed CMOS Logic 3- to 8-Line Decoder/  
Demultiplexer Inverting and Noninverting  
October 1997 - Revised August 2004  
Features  
Ordering Information  
• Select One Of Eight Data Outputs  
Active Low for 138, Active High for 238  
TEMP. RANGE  
o
PART NUMBER  
CD54HC138F3A  
CD54HC238F3A  
CD54HCT138F3A  
CD54HCT238F3A  
CD74HC138E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOP  
[ /Title  
(CD74  
HC138  
,
CD74  
HCT13  
8,  
CD74  
HC238  
,
CD74  
HCT23  
8)  
• l/O Port or Memory Selector  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• Three Enable Inputs to Simplify Cascading  
• Typical Propagation Delay of 13 ns at V  
CC  
= 5 V,  
o
C = 15 pF, T = 25 C  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
CD74HC138M  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
CD74HC138MT  
CD74HC138M96  
CD74HC238E  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
• HC Types  
CD74HC238M  
/Sub-  
ject  
(High  
Speed  
- 2 V to 6 V Operation  
CD74HC238MT  
CD74HC238M96  
CD74HC238NSR  
CD74HC238PW  
CD74HC238PWR  
CD74HC238PWT  
CD74HCT138E  
CD74HCT138M  
CD74HCT138MT  
CD74HCT138M96  
CD74HCT238E  
CD74HCT238M  
CD74HCT238M96  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5 V  
CC  
• HCT Types  
- 4.5-V to 5.5-V Operation  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8 V (Max), V = 2 V (Min)  
IL  
IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
Description  
The ’HC138, ’HC238, ’HCT138, and ’HCT238 are high-speed  
silicon-gate CMOS decoders well suited to memory address  
decoding or data-routing applications. Both circuits feature  
low power consumption usually associated with CMOS  
circuitry, yet have speeds comparable to low-power Schottky  
TTL logic. Both circuits have three binary select inputs (A0,  
A1, and A2). If the device is enabled, these inputs determine  
which one of the eight normally high outputs of the  
HC/HCT138 series go low or which of the normally low  
outputs of the HC/HCT238 series go high.  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
Two active low and one active high enables (E1, E2, and E3)  
are provided to ease the cascading of decoders. The  
decoder’s eight outputs can drive ten low-power Schottky  
TTL equivalent loads.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2004, Texas Instruments Incorporated  
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