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CD54HC109F3A PDF预览

CD54HC109F3A

更新时间: 2024-09-30 22:06:55
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
12页 279K
描述
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

CD54HC109F3A 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.21
Is Samacsys:N系列:HC/UH
JESD-30 代码:R-GDIP-T16长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:J-KBAR FLIP-FLOP
最大频率@ Nom-Sup:20000000 Hz最大I(ol):-0.006 A
位数:2功能数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
最大电源电流(ICC):0.04 mAProp。Delay @ Nom-Sup:53 ns
传播延迟(tpd):265 ns认证状态:Not Qualified
施密特触发器:No筛选级别:38535Q/M;38534H;883B
座面最大高度:5.08 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:6.92 mm
最小 fmax:23 MHzBase Number Matches:1

CD54HC109F3A 数据手册

 浏览型号CD54HC109F3A的Datasheet PDF文件第2页浏览型号CD54HC109F3A的Datasheet PDF文件第3页浏览型号CD54HC109F3A的Datasheet PDF文件第4页浏览型号CD54HC109F3A的Datasheet PDF文件第5页浏览型号CD54HC109F3A的Datasheet PDF文件第6页浏览型号CD54HC109F3A的Datasheet PDF文件第7页 
CD54HC109, CD74HC109,  
CD54HCT109, CD74HCT109  
Data sheet acquired from Harris Semiconductor  
SCHS140E  
Dual J-K Flip-Flop with Set and Reset  
Positive-Edge Trigger  
March 1998 - Revised October 2003  
Features  
Description  
• Asynchronous Set and Reset  
• Schmitt Trigger Clock Inputs  
The ’HC109 and ’HCT109 are dual J-K flip-flops with set and  
reset. The flip-flop changes state with the positive transition  
of Clock (1CP and 2CP).  
[ /Title  
(CD74H  
C109,  
CD74H  
CT109)  
/Subject  
(Dual J-  
K Flip-  
Flop  
• Typical f  
MAX  
= 54MHz at V = 5V, C = 15pF,  
CC L  
The flip-flop is set and reset by active-low S and R,  
respectively. A low on both the set and reset inputs  
simultaneously will force both Q and Q outputs high.  
However, both set and reset going high simultaneously  
results in an unpredictable output condition.  
o
T = 25 C  
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
Ordering Information  
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
TEMP. RANGE  
o
PART NUMBER  
CD54HC109F3A  
CD54HCT109F3A  
CD74HC109E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
with Set  
and  
Reset  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
CD74HC109M  
at V  
= 5V  
CC  
CD74HC109MT  
CD74HC109M96  
CD74HCT109E  
CD74HCT109M  
CD74HCT109MT  
CD74HCT109M96  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
l
OL OH  
Pinout  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
CD54HC109, CD54HCT109  
(CERDIP)  
CD74HC109, CD74HCT109  
(PDIP, SOIC)  
TOP VIEW  
1R  
1J  
1
2
3
4
5
6
7
8
16 V  
CC  
15 2R  
14 2J  
13 2K  
12 2CP  
11 2S  
10 2Q  
1K  
1CP  
1S  
1Q  
1Q  
9
2Q  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

CD54HC109F3A 替代型号

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