Datasheet > CD54ACT109_08

CD54ACT109_08

更新时间： 2024-11-24 05:08:59

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
11页	350K
描述
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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CD54ACT109_08 数据手册

CD54ACT109, CD74ACT109

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SCHS327 – JANUARY 2003

CD54ACT109 . . . F PACKAGE

CD74ACT109 . . . E OR M PACKAGE

(TOP VIEW)

Inputs Are TTL-Voltage Compatible

Speed of Bipolar F, AS, and S, With

Significantly Reduced Power Consumption

1CLR

2CLR

Balanced Propagation Delays

±24-mA Output Drive Current

– Fanout to 15 F Devices

1CLK

1PRE

SCR-Latchup-Resistant CMOS Process and

Circuit Design

2CLK

11 2PRE

Exceeds 2-kV ESD Protection Per

MIL-STD-883, Method 3015

GND

description/ordering information

The ’ACT109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset

(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE

and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to

the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and

isnotdirectlyrelatedtotherisetimeoftheclockpulse. Followingthehold-timeinterval, dataattheJandKinputs

can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle

flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

PDIP – E

SOIC – M

CDIP – F

Tube

CD74ACT109E

CD74ACT109M

CD74ACT109E

–55°C to 125°C

ACT109M

Tape and reel CD74ACT109M96

Tube CD54ACT109F3A

CD54ACT109F3A

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUTS

PRE

CLR

CLK

†

↑

Toggle

↑

‡

Unpredictableand unstable condition if both PRE and CLR

go high simultaneously after both being low at the same

time

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...11

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与CD54ACT109_08相关器件

型号	品牌	获取价格	描述	数据表
CD54ACT109E	ETC	获取价格	Logic IC
CD54ACT109EN	ETC	获取价格	Logic IC
CD54ACT109F	ETC	获取价格	Logic IC
CD54ACT109F3A	TI	获取价格	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
CD54ACT109H	GE	获取价格	J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output
CD54ACT109HX	GE	获取价格	J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output
CD54ACT109M	ETC	获取价格	Logic IC
CD54ACT10E	ETC	获取价格	Logic IC
CD54ACT10EN	ETC	获取价格	Logic IC
CD54ACT10F	ETC	获取价格	Logic IC

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