Datasheet > CD54ACT112_08

CD54ACT112_08

更新时间： 2024-11-24 05:08:59

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
13页	546K
描述
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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CD54ACT112_08 数据手册

CD54ACT112, CD74ACT112

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SCHS323 – JANUARY 2003

CD54ACT112 . . . F PACKAGE

CD74ACT112 . . . M PACKAGE

(TOP VIEW)

Inputs Are TTL-Voltage Compatible

Speed of Bipolar F, AS, and S, With

Significantly Reduced Power Consumption

1CLK

Balanced Propagation Delays

1CLR

2CLR

2CLK

±24-mA Output Drive Current

– Fanout to 15 F Devices

1PRE

SCR-Latchup-Resistant CMOS Process and

Circuit Design

11 2J

Exceeds 2-kV ESD Protection Per

MIL-STD-883, Method 3015

2PRE

GND

description/ordering information

The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset

(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE

and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to

the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and

is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs

may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle

flip-flops by tying J and K high.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

Tube

CD74ACT112M

SOIC – M

CDIP – F

ACT112M

CD54ACT112F3A

–55°C to 125°C

Tape and reel CD74ACT112M96

Tube CD54ACT112F3A

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUTS

PRE

CLR

CLK

‡

↓

Toggle

‡

Output states are unpredictable if PRE and CLR go high

simultaneously after both being low at the same time.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...13

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与CD54ACT112_08相关器件

型号	品牌	获取价格	描述	数据表
CD54ACT112E	ETC	获取价格	Logic IC
CD54ACT112EN	ETC	获取价格	Logic IC
CD54ACT112F	ETC	获取价格	Logic IC
CD54ACT112F3A	TI	获取价格	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
CD54ACT112H	TI	获取价格	ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC
CD54ACT112H	GE	获取价格	J-K Flip-Flop, ACT Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, C
CD54ACT112HX	GE	获取价格	J-K Flip-Flop, ACT Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, C
CD54ACT112M	ETC	获取价格	Logic IC
CD54ACT113A	INTERSIL	获取价格	Dual “J-K” Flip-Flop with Set and Reset
CD54ACT138	INTERSIL	获取价格	3-to-8-Line Decoder/Demultiplexer Inverting

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