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CD4555BFMSR PDF预览

CD4555BFMSR

更新时间: 2024-11-13 21:10:55
品牌 Logo 应用领域
瑞萨 - RENESAS 驱动输出元件
页数 文件大小 规格书
11页 97K
描述
4000/14000/40000 SERIES, OTHER DECODER/DRIVER, TRUE OUTPUT, CDIP16, FRIT SEALED, DIP-16

CD4555BFMSR 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.2
系列:4000/14000/40000输入调节:STANDARD
JESD-30 代码:R-GDIP-T16功能数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
传播延迟(tpd):594 ns认证状态:Not Qualified
筛选级别:MIL-PRF-38535 Class V座面最大高度:5.08 mm
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL总剂量:100k Rad(Si) V
宽度:7.62 mmBase Number Matches:1

CD4555BFMSR 数据手册

 浏览型号CD4555BFMSR的Datasheet PDF文件第2页浏览型号CD4555BFMSR的Datasheet PDF文件第3页浏览型号CD4555BFMSR的Datasheet PDF文件第4页浏览型号CD4555BFMSR的Datasheet PDF文件第5页浏览型号CD4555BFMSR的Datasheet PDF文件第6页浏览型号CD4555BFMSR的Datasheet PDF文件第7页 
CD4555BMS  
CD4556BMS  
CMOS Dual Binary to 1 of 4  
Decoder/Demultiplexers  
December 1992  
CD4556BMS  
TOP VIEW  
Features  
Pinouts  
• High Voltage Type (20V Rating)  
E
A
1
2
3
4
5
6
7
8
16 VDD  
• CD4555BMS: Outputs High on Select  
• CD4556BMS: Outputs Low on Select  
• Expandable with Multiple Packages  
• 100% Tested for Quiescent Current at 20V  
• Standardized, Symmetrical Output Characteristics  
15  
14  
13  
E
A
B
B
Q0  
Q1  
Q2  
Q3  
VSS  
1/2 OF DUAL  
1/2 OF DUAL  
12 Q0  
11 Q1  
10 Q2  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and +25oC  
9
Q3  
• Noise Margin (Over Full Package/Temperature Range)  
- 1V at VDD = 5V  
CD4555BMS  
TOP VIEW  
- 2V at VDD = 10V  
E
A
1
2
3
4
5
6
7
8
16 VDD  
- 2.5V at VDD = 15V  
15  
14  
13  
E
A
B
• 5V, 10V and 15V Parametric Ratings  
B
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
Q0  
Q1  
Q2  
Q3  
VSS  
1/2 OF DUAL  
1/2 OF DUAL  
12 Q0  
11 Q1  
10 Q2  
Applications  
• Decoding  
9
Q3  
• Code Conversion  
• Demultiplexing (Using Enable Input as a Data Input  
• Memory Chip-Enable Selection  
• Function Selection  
Functional Diagrams  
VDD  
16  
4
2
Q0  
A
3
5
6
7
Q1  
Q2  
Q3  
B
E
1
Description  
CD4555BMS and CD4556BMS are dual one-of-four decod-  
ers/demultiplexers. Each decoder has two select inputs (A  
and B), an Enable input (E), and four mutually exclusive out-  
puts. On the CD4555BMS the outputs are high on select; on  
the CD4556BMS the outputs are low on select.  
12  
11  
10  
9
Q0  
Q1  
Q2  
Q3  
14  
A
13  
B
15  
E
8
VSS  
When the Enable input is high, the outputs of the  
CD4555BMS remain low and the outputs of the  
CD4556BMS remain high regardless of the state of the  
select inputs A and B. The CD4555BMS and CD4556BMS  
are similar to types MC14555 and MC14556, respectively.  
CD4555BMS  
VDD  
16  
4
5
6
7
2
3
1
Q0  
Q1  
Q2  
Q3  
A
B
E
The CD4555BMS and CD4556BMS are supplied in these  
16-lead outline packages:  
12  
11  
10  
9
Q0  
Q1  
Q2  
Q3  
14  
13  
15  
A
B
E
Braze Seal DIP  
Frit Seal DIP  
Ceramic Flatpack  
*CD4555B Only  
*H46  
H1E  
H6W  
†H4T  
8
VSS  
†CD4556B Only  
CD4556BMS  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3346  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1249  

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