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CD4527 PDF预览

CD4527

更新时间: 2024-09-30 22:54:23
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英特矽尔 - INTERSIL /
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11页 103K
描述
CMOS BCD Rate Multiplier

CD4527 数据手册

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CD4527BMS  
CMOS BCD Rate Multiplier  
December 1992  
Features  
Description  
• High Voltage Type (20V Rating)  
• Cascadable in Multiples of 4-Bits  
• Set to “9” Input and “9” Detect Output  
• 100% Tested for Quiescent Current at 20V  
• 5V, 10V and 15V Parametric Ratings  
CD4527BMS is a low power 4-bit digital rate multiplier that  
provides an output pulse rate which is the clock input pulse  
rate multiplied by 1/10 times the BCD input. For example,  
when the BCD input is 8, there will be 8 output pulses for  
every 10 input pulses. This device may be used to perform  
arithmetic operations (add, subtract, divide, raise to a  
power), solve algebraic and differential equations, generate  
natural logarithms and trigonometric functions, A/D and D/A  
conversion, and frequency division.  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and +25oC  
For fractional multipliers with more than one digit,  
CD4527BMS devices may be cascaded in two different  
modes: the Add mode and the Multiply mode (see Figures 9  
and 11). In the Add mode,  
• Noise Margin (Over Full Package/Temperature Range)  
- 1V at VDD = 5V  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
Output Rate =  
(Clock Rate) [0.1BCD1 + 0.01BCD2 + 0.001BCD3 + . . .]  
• Standardized Symmetrical Output Characteristics  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
In the Multiply mode, the fraction programmed into the first  
rate multiplier is multiplied by the fraction programmed into  
the second one,  
9
4
36  
e.g.  
x
=
or 36 output  
Applications  
10  
10  
100  
• Numerical Control  
• Instrumentation  
• Digital Filtering  
pulses for every 100 clock input pulses.  
The CD4527BMS is supplied in these 16-lead outline packages:  
Braze Seal DIP  
Frit Seal DIP  
H4X  
H1F  
H6W  
• Frequency Synthesis  
Ceramic Flatpack  
Pinout  
Functional Diagram  
CD4527BMS  
TOP VIEW  
BCD RATE  
SELECT INPUTS  
STROBE  
A
14 15  
B
C
2
D
3
10  
“9” OUT  
1
2
3
4
5
6
7
8
16 VDD  
CLOCK  
11  
CASCADE  
9
12  
C
15 B  
INHIBIT  
D
14 A  
(CARRY) IN  
OUT  
OUT  
RATE  
SELECT  
LOGIC  
6
5
4
SET TO “9”  
13 CLEAR  
12 CASCADE  
11 INHIBIT IN (CARRY)  
10 STROBE  
RATE  
OUTPUTS  
SET TO  
NINE  
÷10  
COUNTER  
OUT  
13  
CLEAR  
OUT  
INHIBIT OUT (CARRY)  
VSS  
“9” OUT  
1
9
CLOCK  
7
INHIBIT  
(CARRY) OUT  
VSS = 8  
VDD = 16  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3343  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1216  

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