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CD4508BFMSR PDF预览

CD4508BFMSR

更新时间: 2024-11-05 14:48:23
品牌 Logo 应用领域
瑞萨 - RENESAS 驱动输出元件逻辑集成电路
页数 文件大小 规格书
9页 87K
描述
4000/14000/40000 SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDIP24, FRIT SEALED, DIP-24

CD4508BFMSR 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:DIP包装说明:FRIT SEALED, DIP-24
针数:24Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.73
Is Samacsys:N系列:4000/14000/40000
JESD-30 代码:R-GDIP-T24JESD-609代码:e0
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.00036 A位数:4
功能数量:2端口数量:2
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP24,.6
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5/15 V
Prop。Delay @ Nom-Sup:351 ns传播延迟(tpd):351 ns
认证状态:Not Qualified筛选级别:MIL-PRF-38535 Class V
座面最大高度:5.72 mm子类别:FF/Latches
最大供电电压 (Vsup):18 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED总剂量:100k Rad(Si) V
宽度:15.24 mmBase Number Matches:1

CD4508BFMSR 数据手册

 浏览型号CD4508BFMSR的Datasheet PDF文件第2页浏览型号CD4508BFMSR的Datasheet PDF文件第3页浏览型号CD4508BFMSR的Datasheet PDF文件第4页浏览型号CD4508BFMSR的Datasheet PDF文件第5页浏览型号CD4508BFMSR的Datasheet PDF文件第6页浏览型号CD4508BFMSR的Datasheet PDF文件第7页 
CD4508BMS  
CMOS Dual 4-Bit Latch  
December 1992  
Features  
Pinout  
CD4508BMS  
TOP VIEW  
• High-Voltage Types (20-Volt Rating)  
• Two Independent 4-Bit Latches  
• Individual Master Reset for Each 4-Bit Latch  
1
2
3
4
5
6
7
8
9
24  
VDD  
RESET A  
23 Q3B  
STROBE A  
• 3-State Outputs with High-Impedance State for Bus  
Line Applications  
22 D3B  
OUTPUT DISABLE A  
21 Q2B  
D0A  
Q0A  
D1A  
Q1A  
• Medium-Speed Operation: tPHL = tPLH = 70nS (Typ.)  
at VDD = 10V and CL = 50pF  
20 D2B  
19 Q1B  
• 100% Tested for Quiescent Current at 20V  
• 5V, 10V, and 15V Parametric Ratings  
18 D1B  
17 Q0B  
D2A  
Q2A  
16 D0B  
• Standardized, Symmetrical Output Characteristics  
D3A 10  
Q3A 11  
VSS 12  
15 OUTPUT DISABLE B  
14 STROBE B  
13 RESET B  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and 25oC  
• Noise Margin (Full Package-Temperature Range):  
- 1V at VDD = 5V  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
Functional Diagram  
• Meets all Requirements of JEDEC Tentative Standard  
No. 13B, "Standard Specifications for Description of  
‘B’ Series CMOS Devices"  
OUTPUT  
DISABLE  
D0A  
Q0A  
D1A  
Q1A  
Applications  
4-BIT  
LATCH  
3-STATE  
OUTUTS  
Q2A  
D2A  
D3A  
• Buffer Storage  
Q3A  
• Holding Registers  
• Data Storage and Multiplexing  
STROBE  
RESET  
OUTPUT  
DISABLE  
Description  
D0B  
D1B  
Q0B  
CD4508BMS dual 4-bit latch contains two identical 4-bit  
latches with separate STROBE, RESET, and OUTPUT  
DISABLE controls. With the STROBE line in the high state,  
the data on the "D" inputs appear at the corresponding "Q"  
outputs provided the DISABLE line is in the low state.  
Changing the STROBE line to the low state locks the data  
into the latch. A high on the reset line forces the outputs to a  
low level regardless of the state of the STROBE input. The  
outputs are forced to the high-impedance state for bus line  
applications by a high level on the DISABLE input.  
Q1B  
4-BIT  
LATCH  
3-STATE  
OUTUTS  
Q2B  
D2B  
Q3B  
D3B  
STROBE  
RESET  
The CD4508BMS is supplied in these 24 lead outline  
packages:  
Braze Seal DIP  
Frit Seal DIP  
H4V  
H1Z  
Ceramic Flatpack H4P  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3337  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1148  

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