Datasheet > CD4508BMS

CD4508BMS

更新时间： 2024-09-14 22:54:23

品牌	Logo	应用领域
英特矽尔 - INTERSIL		锁存器
页数	文件大小	规格书
9页	88K
描述
CMOS Dual 4-Bit Latch

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中文翻译

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数据手册

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CD4508BMS 数据手册

CD4508BMS

CMOS Dual 4-Bit Latch

December 1992

Features

Pinout

CD4508BMS

TOP VIEW

• High-Voltage Types (20-Volt Rating)

• Two Independent 4-Bit Latches

• Individual Master Reset for Each 4-Bit Latch

VDD

RESET A

23 Q3B

STROBE A

• 3-State Outputs with High-Impedance State for Bus

Line Applications

22 D3B

OUTPUT DISABLE A

21 Q2B

D0A

Q0A

D1A

Q1A

• Medium-Speed Operation: tPHL = tPLH = 70nS (Typ.)

at VDD = 10V and CL = 50pF

20 D2B

19 Q1B

• 100% Tested for Quiescent Current at 20V

• 5V, 10V, and 15V Parametric Ratings

18 D1B

17 Q0B

D2A

Q2A

16 D0B

• Standardized, Symmetrical Output Characteristics

D3A 10

Q3A 11

VSS 12

15 OUTPUT DISABLE B

14 STROBE B

13 RESET B

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and 25^oC

• Noise Margin (Full Package-Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

Functional Diagram

• Meets all Requirements of JEDEC Tentative Standard

No. 13B, "Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices"

OUTPUT

DISABLE

D0A

Q0A

D1A

Q1A

Applications

4-BIT

LATCH

3-STATE

OUTUTS

Q2A

D2A

D3A

• Buffer Storage

Q3A

• Holding Registers

• Data Storage and Multiplexing

STROBE

RESET

OUTPUT

DISABLE

Description

D0B

D1B

Q0B

CD4508BMS dual 4-bit latch contains two identical 4-bit

latches with separate STROBE, RESET, and OUTPUT

DISABLE controls. With the STROBE line in the high state,

the data on the "D" inputs appear at the corresponding "Q"

outputs provided the DISABLE line is in the low state.

Changing the STROBE line to the low state locks the data

into the latch. A high on the reset line forces the outputs to a

low level regardless of the state of the STROBE input. The

outputs are forced to the high-impedance state for bus line

applications by a high level on the DISABLE input.

Q1B

4-BIT

LATCH

3-STATE

OUTUTS

Q2B

D2B

Q3B

D3B

STROBE

RESET

The CD4508BMS is supplied in these 24 lead outline

packages:

Braze Seal DIP

Frit Seal DIP

H4V

H1Z

Ceramic Flatpack H4P

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3337

7-1148

12 3 4 5 6 7...9

中文翻译

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