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CD4510BFMSR PDF预览

CD4510BFMSR

更新时间： 2024-11-06 14:48:23
品牌 Logo 应用领域
瑞萨 - RENESAS 逻辑集成电路触发器
页数 文件大小 规格书
11页 141K
描述
4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, CDIP16, FRIT SEALED, DIP-16

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CD4510BFMSR 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：DIP包装说明：FRIT SEALED, DIP-16
针数：16Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.4
Is Samacsys：N计数方向：BIDIRECTIONAL
系列：4000/14000/40000JESD-30 代码：R-GDIP-T16
JESD-609代码：e0长度：9.585 mm
负载电容（CL）：50 pF负载/预设输入：YES
逻辑集成电路类型：DECADE COUNTER最大频率@ Nom-Sup：2000000 Hz
最大I（ol）：0.00036 A工作模式：SYNCHRONOUS
位数：4功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5/15 V
Prop。Delay @ Nom-Sup：864 ns传播延迟（tpd）：540 ns
认证状态：Not Qualified筛选级别：MIL-PRF-38535 Class V
座面最大高度：5.33 mm子类别：Counters
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED总剂量：100k Rad(Si) V
触发器类型：POSITIVE EDGE宽度：7.62 mm
最小 fmax：1.48 MHzBase Number Matches：1

CD4510BFMSR 数据手册

 浏览型号CD4510BFMSR的Datasheet PDF文件第2页浏览型号CD4510BFMSR的Datasheet PDF文件第3页浏览型号CD4510BFMSR的Datasheet PDF文件第4页浏览型号CD4510BFMSR的Datasheet PDF文件第5页浏览型号CD4510BFMSR的Datasheet PDF文件第6页浏览型号CD4510BFMSR的Datasheet PDF文件第7页 
CD4510BMS, CD4516BMS  
Data Sheet  
December 1992  
File Number 3338  
CMOS Presettable Up/Down Counters  
Features  
• High Voltage Types (20V Rating)  
• CD4510BMS - BCD Type  
CD4510BMS Presettable BCD Up/Down Counter and the  
CD4516BMS Presettable Binary Up/Down counter consist of  
four synchronously clocked D-type flip-flops (with a gating  
structure to provide T-type flip-flop capability) connected as  
counters. These counters can be cleared by a high level on  
the RESET line, and can be preset to any binary number  
present on the jam inputs by a high level on the PRESET  
ENABLE line. The CD4510BMS will count out of non-BCD  
counter states in a maximum of two clock pulses in the up  
mode, and a maximum of four clock pulses in the down mode.  
• CD4516BMS - Binary Type  
• Medium Speed Operation  
- fCL = 8MHz Typ. at 10V  
• Synchronous Internal Carry Propagation  
• Reset and Preset Capability  
• 100% Tested for Quiescent Current at 20V  
• 5V, 10V and 15V Parametric Ratings  
If the CARRY IN input is held low, the counter advances up or  
down on each positive-going clock transition. Synchronous  
cascading is accomplished by connecting all clock inputs in  
parallel and connecting the CARRY OUT of a less significant  
stage to the CARRY IN of a more significant stage.  
• Standardized Symmetrical Output Characteristics  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
o
age Temperature Range; 100nA at 18V and +25 C  
The CD4510BMS and CD4516BMS can be cascaded in the  
ripple mode by connecting the CARRY OUT to the clock of  
the next stage. If the UP/DOWN input changes during a ter-  
minal count, the CARRY OUT must be gated with the clock,  
and the UP/DOWN input must change while the clock is  
high. This method provides a clean clock signal to the sub-  
sequent counting stage. (See Figures 13, 14.)  
• Noise Margin (Over Full Package/Temperature Range)  
- 1V at VDD = 5V  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
These devices are similar to types MC14510 and MC14516.  
The CD4510BMS and CD4516BMS are supplied in these  
16-lead outline packages:  
Applications  
• Up/Down Difference Counting  
• Multistage Synchronous Counting  
• Multistage Ripple Counting  
• Synchronous Frequency Dividers  
Braze Seal DIP  
Frit Seal DIP  
Ceramic Flatpack  
*CD4510B Only  
*H4W †H45  
*FBF  
H6W  
†H1F  
†CD4516B Only  
Pinout  
Functional Diagram  
CD4510BMS, CD4516BMS  
PRESET ENABLE  
TOP VIEW  
1
4
12  
13  
3
6
11  
14  
2
P1  
P2  
P3  
P4  
Q1  
Q2  
Q3  
Q4  
PRESET ENABLE  
1
2
3
4
5
6
7
8
16 VDD  
15 CLOCK  
14 Q3  
Q4  
P4  
P1  
13 P3  
CARRY IN  
Q1  
12 P2  
11 Q2  
15  
10  
5
CLOCK  
UP/DOWN  
CARRY IN  
10 UP/DOWN  
CARRY OUT  
VSS  
7
9
RESET  
CARRY OUT  
9
VDD = 16  
VSS = 8  
RESET  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
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