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CD4070BCN PDF预览

CD4070BCN

更新时间: 2024-09-23 22:54:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
5页 56K
描述
Quad 2-Input EXCLUSIVE-OR Gate

CD4070BCN 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.08
系列:4000/14000/40000JESD-30 代码:R-PDIP-T14
JESD-609代码:e3长度:19.18 mm
负载电容(CL):50 pF逻辑集成电路类型:XOR GATE
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT APPLICABLE电源:5/15 V
Prop。Delay @ Nom-Sup:185 ns传播延迟(tpd):185 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:5.08 mm子类别:Gates
最大供电电压 (Vsup):15 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Matte Tin (Sn)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT APPLICABLE宽度:7.62 mm
Base Number Matches:1

CD4070BCN 数据手册

 浏览型号CD4070BCN的Datasheet PDF文件第2页浏览型号CD4070BCN的Datasheet PDF文件第3页浏览型号CD4070BCN的Datasheet PDF文件第4页浏览型号CD4070BCN的Datasheet PDF文件第5页 
October 1987  
Revised January 1999  
CD4070BC  
Quad 2-Input EXCLUSIVE-OR Gate  
protected from damage due to static discharge by diode  
General Description  
clamps to VDD and VSS  
.
The CD4070BC employs complementary MOS (CMOS)  
transistors to achieve wide power supply operating range,  
low power consumption, and high noise margin, the  
CD4070BC provide basic functions used in the implemen-  
tation of digital integrated circuit systems. The N- and P-  
channel enhancement mode transistors provide a symmet-  
rical circuit with output swing essentially equal to the supply  
voltage. No DC power other than that caused by leakage  
current is consumed during static condition. All inputs are  
Features  
Wide supply voltage range: 3.0V to 15V  
High noise immunity: 0.45 VDD typ.  
Low power TTL compatibility:  
Fan out of 2 driving 74L or 1 driving 74LS  
Pin compatible to CD4030A  
Equivalent to MM74C86 and MC14070B  
Ordering Code:  
Order Number Package Number  
Package Description  
CD4070BCM  
M14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
CD4070BCN  
N14A  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Truth Table  
Inputs  
Outputs  
Pin Assignments for SOIC and DIP  
A
L
B
L
Y
L
L
H
L
H
H
L
H
H
H
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005976.prf  
www.fairchildsemi.com  

CD4070BCN 替代型号

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