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CD4050BFMSR PDF预览

CD4050BFMSR

更新时间： 2024-11-04 21:07:11
品牌 Logo 应用领域
瑞萨 - RENESAS 栅输入元件逻辑集成电路触发器
页数 文件大小 规格书
8页 201K
描述
4000/14000/40000 SERIES, HEX 1-INPUT NON-INVERT GATE, CDIP14, FRIT SEALED, DIP-14

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CD4050BFMSR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：14Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.65
系列：4000/14000/40000JESD-30 代码：R-GDIP-T14
JESD-609代码：e0负载电容（CL）：50 pF
逻辑集成电路类型：BUFFER最大I（ol）：0.00036 A
功能数量：6输入次数：1
端子数量：14最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5/15 V
Prop。Delay @ Nom-Sup：189 ns传播延迟（tpd）：189 ns
认证状态：Not Qualified施密特触发器：NO
筛选级别：MIL-PRF-38535 Class V座面最大高度：5.08 mm
子类别：Gates标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
总剂量：100k Rad(Si) V宽度：7.62 mm
Base Number Matches：1

CD4050BFMSR 数据手册

 浏览型号CD4050BFMSR的Datasheet PDF文件第2页浏览型号CD4050BFMSR的Datasheet PDF文件第3页浏览型号CD4050BFMSR的Datasheet PDF文件第4页浏览型号CD4050BFMSR的Datasheet PDF文件第5页浏览型号CD4050BFMSR的Datasheet PDF文件第6页浏览型号CD4050BFMSR的Datasheet PDF文件第7页 
CD4050BMS  
TM  
Data Sheet  
December 1992  
FN3193  
CMOS Hex Buffer/Converter  
Features  
• High Voltage Type (20V Rating)  
• Non-Inverting Type  
The CD4050BMS is an non-inverting hex buffer and features  
logic level conversion using only one supply voltage (VCC).  
The input signal high level (VIH) can exceed the VCC supply  
voltage when this device is used for logic level conversions.  
This device is intended for use as CMOS to DTL/TTL  
converters and can drive directly two DTL/TTL loads. (VCC  
= 5V, VOL ≤ 0.4V, and IOL ≥ 3.3mA.  
• High Sink Current for Driving 2 TTL Loads  
• High-to-Low Level Logic Conversion  
• 100% Tested for Quiescent Current at 20V  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
The CD4050BMS is designated as replacement for  
CD4010B. Because the CD4050BMS requires only one  
power supply, it is preferred over the CD4010B and should  
be used in place of the CD4010B in all inverter, current  
driver, or logic level conversion applications. In these appli-  
cations the CD4050BMS is pin compatible with the  
CD4010B, and can be substituted for this device in existing  
as well as in new designs. Terminal No. 16 is not connected  
internally on the CD4050BMS, therefore, connection to this  
terminal is of no consequence to circuit operation. For appli-  
cations not requiring high sink current or voltage conversion,  
the CD4069UB Hex Inverter is recommended.  
o
age Temperature Range; 100nA at 18V and +25 C  
• 5V, 10V and 15V Parametric Ratings  
Applications  
• CMOS to DTL/TTL Hex Converter  
• CMOS Current “Sink” or “Source” Driver  
• CMOS High-to-Low Logic Level Converter  
Pinout  
CD4050BMS  
The CD4050BMS is supplied in these 16 lead outline pack-  
ages:  
TOP VIEW  
VCC  
G = A  
A
1
2
3
4
5
6
7
8
16 NC  
Braze Seal DIP  
Frit Seal DIP  
H4T  
H1E  
15 L = F  
14  
F
Ceramic Flatpack H3X  
H = B  
B
13 NC  
12 K = E  
I = C  
C
11  
E
10 J = D  
9
D
VSS  
Functional Diagram  
Schematic Diagram  
VCC  
3
5
2
A
G = A  
H = B  
I = C  
4
B
C
D
E
F
P
N
P
N
7
6
R
IN  
OUT  
9
10  
12  
15  
J = D  
K = E  
L = F  
1
8
VCC  
VSS  
11  
14  
VSS  
NC = 13  
NC = 16  
FIGURE 1. SCHEMATIC DIAGRAM, 1 OF 6 IDENTICAL UNITS  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.  
Copyright © Intersil Americas Inc. 2002. All Rights Reserved  
4-1  
12345678

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