Datasheet > CD4050BMS

CD4050BMS

更新时间： 2024-10-01 22:54:19

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英特矽尔 - INTERSIL		转换器逻辑集成电路
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7页	85K
描述
CMOS Hex Buffer/Converter

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CD4050BMS 数据手册

CD4050BMS

December 1992

File Number 3193

CMOS Hex Buffer/Converter

Features

• High Voltage Type (20V Rating)

• Non-Inverting Type

The CD4050BMS is an non-inverting hex buffer and features

logic level conversion using only one supply voltage (VCC).

The input signal high level (VIH) can exceed the VCC supply

voltage when this device is used for logic level conversions.

This device is intended for use as CMOS to DTL/TTL

converters and can drive directly two DTL/TTL loads. (VCC

= 5V, VOL ≤ 0.4V, and IOL ≥ 3.3mA.

• High Sink Current for Driving 2 TTL Loads

• High-to-Low Level Logic Conversion

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Pack-

The CD4050BMS is designated as replacement for

CD4010B. Because the CD4050BMS requires only one

power supply, it is preferred over the CD4010B and should

be used in place of the CD4010B in all inverter, current

driver, or logic level conversion applications. In these appli-

cations the CD4050BMS is pin compatible with the

CD4010B, and can be substituted for this device in existing

as well as in new designs. Terminal No. 16 is not connected

internally on the CD4050BMS, therefore, connection to this

terminal is of no consequence to circuit operation. For appli-

cations not requiring high sink current or voltage conversion,

the CD4069UB Hex Inverter is recommended.

age Temperature Range; 100nA at 18V and +25 C

• 5V, 10V and 15V Parametric Ratings

Applications

• CMOS to DTL/TTL Hex Converter

• CMOS Current “Sink” or “Source” Driver

• CMOS High-to-Low Logic Level Converter

Pinout

CD4050BMS

The CD4050BMS is supplied in these 16 lead outline pack-

ages:

TOP VIEW

VCC

G = A

16 NC

Braze Seal DIP

Frit Seal DIP

H4T

H1E

15 L = F

Ceramic Flatpack H3X

H = B

13 NC

12 K = E

I = C

10 J = D

VSS

Functional Diagram

Schematic Diagram

VCC

G = A

H = B

I = C

OUT

J = D

K = E

L = F

VCC

VSS

NC = 13

NC = 16

FIGURE 1. SCHEMATIC DIAGRAM, 1 OF 6 IDENTICAL UNITS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

4-1

12 3 4 5 6 7

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