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CD4042BM PDF预览

CD4042BM

更新时间: 2024-11-15 22:54:19
品牌 Logo 应用领域
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页数 文件大小 规格书
6页 126K
描述
Quad Clocked D Latch

CD4042BM 数据手册

 浏览型号CD4042BM的Datasheet PDF文件第2页浏览型号CD4042BM的Datasheet PDF文件第3页浏览型号CD4042BM的Datasheet PDF文件第4页浏览型号CD4042BM的Datasheet PDF文件第5页浏览型号CD4042BM的Datasheet PDF文件第6页 
March 1988  
CD4042BM/CD4042BC Quad Clocked D Latch  
General Description  
Features  
Y
Wide supply voltage range  
3.0V to 15V  
0.45 V (typ.)  
The CD4042BM/CD4042BC quad clocked ‘‘D’’ latch is a  
monolithic complementary MOS (CMOS) integrated circuit  
constructed with P- and N-channel enhancement mode  
transistors. The outputs Q and Q either latch or follow the  
data input depending on the clock level which is pro-  
Y
High noise immunity  
DD  
Y
Low power TTL  
compatibility  
Fan out of 2 driving 74L  
or 1 driving 74LS  
Y
Clock polarity control  
e
tion present at the data input is transferred to Q and Q  
grammed by the polarity input. For polarity  
0; the informa-  
Y
Fully buffered data inputs  
Y
Q and Q outputs  
e
during 0 clock level; and for polarity  
during the 1 clock level. When a clock transition occurs  
1, the transfer occurs  
e
e
1), the  
(positive for polarity  
0 and negative for polarity  
information present at the input during the clock transition is  
retained at the outputs until an opposite clock transition oc-  
curs.  
Connection Diagram  
Truth Table  
Dual-In-Line Package  
Clock  
Polarity  
Q
0
0
0
1
1
D
L
1
Latch  
D
K
Latch  
Order Number CD4042B  
TL/F/5966–1  
Top View  
Logic Diagrams  
TL/F/5966–2  
TL/F/5966–3  
TL/F/5966–4  
C
1995 National Semiconductor Corporation  
TL/F/5966  
RRD-B30M105/Printed in U. S. A.  

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