CD4042BMJ

更新时间： 2024-11-16 13:02:43

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
6页	126K
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数据手册

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CD4042BMJ 数据手册

March 1988

CD4042BM/CD4042BC Quad Clocked D Latch

General Description

Features

Wide supply voltage range

3.0V to 15V

0.45 V (typ.)

The CD4042BM/CD4042BC quad clocked ‘‘D’’ latch is a

monolithic complementary MOS (CMOS) integrated circuit

constructed with P- and N-channel enhancement mode

transistors. The outputs Q and Q either latch or follow the

data input depending on the clock level which is pro-

High noise immunity

Low power TTL

compatibility

Fan out of 2 driving 74L

or 1 driving 74LS

Clock polarity control

tion present at the data input is transferred to Q and Q

grammed by the polarity input. For polarity

0; the informa-

Fully buffered data inputs

Q and Q outputs

during 0 clock level; and for polarity

during the 1 clock level. When a clock transition occurs

1, the transfer occurs

1), the

(positive for polarity

0 and negative for polarity

information present at the input during the clock transition is

retained at the outputs until an opposite clock transition oc-

curs.

Connection Diagram

Truth Table

Dual-In-Line Package

Clock

Polarity

Latch

Order Number CD4042B

TL/F/5966–1

Top View

Logic Diagrams

TL/F/5966–2

TL/F/5966–3

TL/F/5966–4

1995 National Semiconductor Corporation

TL/F/5966

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

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CD4042BMS	RENESAS	获取价格	CMOS Quad D Latch, Clocked
CD4042BMW	TI	获取价格	暂无描述
CD4042BNSR	TI	获取价格	CMOS Quad Clocked D Latch
CD4042BNSRE4	TI	获取价格	4000/14000/40000 SERIES, NEGATIVE EDGE TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16, GR
CD4042BNSRE4	ROCHESTER	获取价格	D Latch, 4000/14000/40000 Series, 1-Func, Negative Edge Triggered, 4-Bit, Complementary Ou
CD4042BNSRG4	ROCHESTER	获取价格	D Latch, 4000/14000/40000 Series, 1-Func, Negative Edge Triggered, 4-Bit, Complementary Ou
CD4042BPW	TI	获取价格	CMOS Quad Clocked D Latch
CD4042BPWG4	ROCHESTER	获取价格	D Latch, 4000/14000/40000 Series, 1-Func, Negative Edge Triggered, 4-Bit, Complementary Ou
CD4042BPWG4	TI	获取价格	CMOS Quad Clocked 'D' Latch 16-TSSOP -55 to 125