October 1987
Revised January 1999
CD4043BC • CD4044BC
Quad 3-STATE NOR R/S Latches •
Quad 3-STATE NAND R/S Latches
General Description
Features
■ Wide supply voltage range: 3V to 15V
The CD4043BC are quad cross-couple 3-STATE CMOS
NOR latches, and the CD4044BC are quad cross-couple 3-
STATE CMOS NAND latches. Each latch has a separate Q
output and individual SET and RESET inputs. There is a
common 3-STATE ENABLE input for all four latches. A
logic “1” on the ENABLE input connects the latch states to
the Q outputs. A logic “0” on the ENABLE input discon-
nects the latch states from the Q outputs resulting in an
open circuit condition on the Q output. The 3-STATE fea-
ture allows common bussing of the outputs.
■ Low power: 100 nW (typ.)
■ High noise immunity: 0.45 VDD (typ.)
■ Separate SET and RESET inputs for each latch
■ NOR and NAND configuration
■ 3-STATE output with common output enable
Applications
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•
•
•
Multiple bus storage
Strobed register
Four bits of independent storage with output enable
General digital logic
Ordering Code:
Order Number Package Number
Package Description
CD4043BCM
CD4043BCN
CD4044BCM
CD4044BCSJ
CD4044BCN
M16A
N16E
M16A
M16D
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC and SOP
CD4043BC
Pin Assignments for DIP and SOIC
CD4044BC
Top View
Top View
© 1999 Fairchild Semiconductor Corporation
DS005967.prf
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