CD4034BC

更新时间： 2024-11-17 22:54:19

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
12页	200K
描述
8-Stage TRI-STATE Bidirectional Parallel/Serial Input/Output Bus Register

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CD4034BC 数据手册

February 1988

CD4034BM/CD4034BC 8-Stage TRI-STATE Bidirectional

Parallel/Serial Input/Output Bus Register

General Description

The CD4034BM/CD4034BC is an 8-bit CMOS static shift

which, when combined with serial shifting operations, can

be used to (1) bidirectionally transfer parallel data between

two buses, (2) convert serial data to parallel form and direct

them to either of two buses, (3) store (recirculate) parallel

data, or (4) accept parallel data from either of two buses

and convert them to serial form. These operations are con-

trolled by five control inputs:

All register stages are D-type master-slave flip-flops with

separate master and slave clock inputs generated internally

to allow synchronous or asynchronous data transfer from

master to slave.

All inputs are protected against damage due to static dis-

charge by diode clamps to V

and V

Features

Wide supply voltage range

High noise immunity

Low power TTL

3.0V to 18V

0.45 V (typ.)

A ENABLE (AE): ‘‘A’’ data port is enabled only when AE

is at logical ‘‘1’’. This allows the use of a common bus

for multiple packages.

Fan out of 2 driving 74L

or 1 driving 74LS

compatibility

A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B): This input

controls the direction of data flow. When at logical ‘’1’’,

data flows from port A to B (A is input, B is output).

When at logical ‘‘0’’, the data flow direction is reversed.

RCA CD4034B second source

Applications

Parallel Input/Parallel Output

Parallel Input/Serial Output

Serial Input/Parallel Output

Serial Input/Serial Output register

Shift right/shift left register

ASYNCHRONOUS/SYNCHRONOUS (A/S): When A/S

is at logical ‘‘0’’, data transfer occurs at positive tran-

sition of the CLOCK. When A/S is at logical ‘‘1’’, data

transfer is independent of the CLOCK for parallel opera-

tion. In serial mode, A/S input is internally disabled such

that operation is always synchronous. (Asynchronous

serial operation is not possible.)

Shift right/shift left with parallel loading

Address register

Buffer register

PARALLEL/SERIAL (P/S): A logical ‘‘1’’ P/S input al-

lows data transfer into the registers via A or B port (syn-

Bus system register with enable parallel lines at bus

side

logical ‘‘0’’, asynchronous if A/S

chronous if A/S

Double bus register system

logical ‘‘1’’). A logical ‘‘0’’ P/S allows serial data to

transfer into the register synchronously with the positive

transition of the CLOCK, independent of the A/S input.

Up-down Johnson or ring counter

Pseudo-random code generators

Sample and hold register (storage, counting, display)

Frequency and phase comparator

CLOCK: Single phase, enabled only in synchronous

logical ‘‘0’’

logical ‘‘0’’.

mode. (Either P/S

logical ‘‘1’’ and A/S

or P/S

Connection Diagram

Dual-In-Line Package

Order Number CD4034B

TL/F/5963–1

Top View

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

1995 National Semiconductor Corporation

TL/F/5963

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6 7...12

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与CD4034BC相关器件

型号	品牌	获取价格	描述	数据表
CD4034BCJ	TI	获取价格	4000/14000/40000 SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE
CD4034BCJ/A+	TI	获取价格	IC,SHIFT REGISTER,CMOS,DIP,24PIN,CERAMIC
CD4034BCN	NSC	获取价格	IC 4000/14000/40000 SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, T
CD4034BCN	TI	获取价格	4000/14000/40000 SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE
CD4034BCN/A+	TI	获取价格	IC,SHIFT REGISTER,CMOS,DIP,24PIN,PLASTIC
CD4034BD	TI	获取价格	4000/14000/40000 SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE
CD4034BD3	RENESAS	获取价格	Parallel In Parallel Out, 4000/14000/40000 Series, 8-Bit, Bidirectional, True Output, CMOS
CD4034BE	TI	获取价格	CMOS 8-Stage Static Bidirectional Parallel/Serial
CD4034BE	RENESAS	获取价格	IC,SHIFT REGISTER,CMOS,DIP,24PIN,PLASTIC
CD4034BE98	RENESAS	获取价格	CD4034BE98

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