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CD4034BCN PDF预览

CD4034BCN

更新时间： 2024-11-04 20:41:15
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
12页 198K
描述
4000/14000/40000 SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP24, PLASTIC, DIP-24

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CD4034BCN 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP24,.6Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.49
其他特性：TWO PARALLEL BIDIRECTIONAL DATA PORTS; BIDIRECTIONALLY TRANSFER PARALLEL DATA BETWEEN TWO BUSES计数方向：BIDIRECTIONAL
系列：4000/14000/40000JESD-30 代码：R-PDIP-T24
JESD-609代码：e0长度：31.915 mm
负载电容（CL）：50 pF逻辑集成电路类型：PARALLEL IN PARALLEL OUT
最大频率@ Nom-Sup：2000000 Hz位数：8
功能数量：1端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP24,.6封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5/15 V传播延迟（tpd）：700 ns
认证状态：Not Qualified座面最大高度：5.334 mm
子类别：Shift Registers最大供电电压 (Vsup)：15 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：15.24 mm
最小 fmax：2 MHzBase Number Matches：1

CD4034BCN 数据手册

 浏览型号CD4034BCN的Datasheet PDF文件第2页浏览型号CD4034BCN的Datasheet PDF文件第3页浏览型号CD4034BCN的Datasheet PDF文件第4页浏览型号CD4034BCN的Datasheet PDF文件第5页浏览型号CD4034BCN的Datasheet PDF文件第6页浏览型号CD4034BCN的Datasheet PDF文件第7页 
February 1988  
CD4034BM/CD4034BC 8-Stage TRI-STATE Bidirectional  
É
Parallel/Serial Input/Output Bus Register  
General Description  
The CD4034BM/CD4034BC is an 8-bit CMOS static shift  
register with two parallel bidirectional data ports (A and B)  
which, when combined with serial shifting operations, can  
be used to (1) bidirectionally transfer parallel data between  
two buses, (2) convert serial data to parallel form and direct  
them to either of two buses, (3) store (recirculate) parallel  
data, or (4) accept parallel data from either of two buses  
and convert them to serial form. These operations are con-  
trolled by five control inputs:  
All register stages are D-type master-slave flip-flops with  
separate master and slave clock inputs generated internally  
to allow synchronous or asynchronous data transfer from  
master to slave.  
All inputs are protected against damage due to static dis-  
.
SS  
charge by diode clamps to V  
and V  
DD  
Features  
Y
Wide supply voltage range  
High noise immunity  
Low power TTL  
3.0V to 18V  
0.45 V (typ.)  
A ENABLE (AE): ‘‘A’’ data port is enabled only when AE  
is at logical ‘‘1’’. This allows the use of a common bus  
for multiple packages.  
Y
Y
DD  
Fan out of 2 driving 74L  
or 1 driving 74LS  
compatibility  
A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B): This input  
controls the direction of data flow. When at logical ‘’1’’,  
data flows from port A to B (A is input, B is output).  
When at logical ‘‘0’’, the data flow direction is reversed.  
Y
RCA CD4034B second source  
Applications  
Y
Parallel Input/Parallel Output  
Parallel Input/Serial Output  
Serial Input/Parallel Output  
Serial Input/Serial Output register  
Shift right/shift left register  
ASYNCHRONOUS/SYNCHRONOUS (A/S): When A/S  
is at logical ‘‘0’’, data transfer occurs at positive tran-  
sition of the CLOCK. When A/S is at logical ‘‘1’’, data  
transfer is independent of the CLOCK for parallel opera-  
tion. In serial mode, A/S input is internally disabled such  
that operation is always synchronous. (Asynchronous  
serial operation is not possible.)  
Y
Y
Y
Y
Y
Shift right/shift left with parallel loading  
Address register  
Buffer register  
PARALLEL/SERIAL (P/S): A logical ‘‘1’’ P/S input al-  
lows data transfer into the registers via A or B port (syn-  
Bus system register with enable parallel lines at bus  
side  
e
e
logical ‘‘0’’, asynchronous if A/S  
chronous if A/S  
Y
Y
Y
Y
Y
Double bus register system  
logical ‘‘1’’). A logical ‘‘0’’ P/S allows serial data to  
transfer into the register synchronously with the positive  
transition of the CLOCK, independent of the A/S input.  
Up-down Johnson or ring counter  
Pseudo-random code generators  
Sample and hold register (storage, counting, display)  
Frequency and phase comparator  
CLOCK: Single phase, enabled only in synchronous  
e
logical ‘‘0’’  
e
logical ‘‘0’’.  
mode. (Either P/S  
e
logical ‘‘1’’ and A/S  
or P/S  
Connection Diagram  
Dual-In-Line Package  
Order Number CD4034B  
TL/F/5963–1  
Top View  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/5963  
RRD-B30M105/Printed in U. S. A.  
1234567...12

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与CD4034BCN相关器件

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CD4034BCN/A+ TI

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 		IC,SHIFT REGISTER,CMOS,DIP,24PIN,PLASTIC
CD4034BD TI

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 		4000/14000/40000 SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE
CD4034BD3 RENESAS

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 		Parallel In Parallel Out, 4000/14000/40000 Series, 8-Bit, Bidirectional, True Output, CMOS
CD4034BE TI

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 		CMOS 8-Stage Static Bidirectional Parallel/Serial
CD4034BE RENESAS

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 		IC,SHIFT REGISTER,CMOS,DIP,24PIN,PLASTIC
CD4034BE98 RENESAS

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 		CD4034BE98
CD4034BEE4 TI

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 		CMOS 8-Stage Static Bidirectional Parallel/Serial
CD4034BEX RENESAS

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 		IC,SHIFT REGISTER,CMOS,DIP,24PIN,PLASTIC
CD4034BF TI

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 		4000/14000/40000 SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE
CD4034BF RENESAS

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 		IC,SHIFT REGISTER,CMOS,DIP,24PIN,CERAMIC

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