CD4031BCJ/A+

更新时间： 2024-11-04 13:02:43

品牌	Logo	应用领域
美国国家半导体 - NSC		移位寄存器
页数	文件大小	规格书
6页	148K
描述
IC,SHIFT REGISTER,CMOS,DIP,16PIN,CERAMIC

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中文翻译

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技术参数
数据手册

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CD4031BCJ/A+ 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	风险等级：	5.92
Is Samacsys：	N	JESD-30 代码：	R-XDIP-T16
JESD-609代码：	e0	位数：	64
功能数量：	1	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	CERAMIC	封装代码：	DIP
封装等效代码：	DIP16,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	电源：	5/15 V
子类别：	Shift Registers	表面贴装：	NO
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
Base Number Matches：	1

CD4031BCJ/A+ 数据手册

February 1988

CD4031BM/CD4031BC

64-Stage Static Shift Register

General Description

Features

Wide supply voltage range

3.0V to 15V

0.45 V (typ.)

The CD4031BM/CD4031BC is an integrated, complemen-

tary MOS (CMOS), 64-stage, fully static shift register. Two

data inputs, DATA IN and RECIRCULATE IN, and a MODE

CONTROL input are provided. Data at the DATA input

(when MODE CONTROL is low) or data at the RECIRCU-

LATE input (when MODE CONTROL is high), which meets

the setup and hold time requirements, is entered into the

first stage of the register and is shifted one stage at each

positive transition of the CLOCK.

High noise immunity

Low power TTL

compatibility

fan out of 2 driving 74L

or 1 driving 74LS

DC to 8 MHz

Fully static operation

10V (typ.)

5 pF (typ.)

input capacitance

Fully buffered clock input

Single phase clocking requirements

Data output is available in both true and complement forms

from the 64th stage. Both the DATA OUT (Q) AND DATA

OUT (Q) outputs are fully buffered.

Delayed clock output for reduced clock drive require-

ments

Fully buffered outputs

The CLOCK input of the CD4031BM/CD4031BC is fully

buffered, and present only a standard input load capaci-

High current sinking capability

Q output

1.6 mA

5V and 25 C

tance. However, a DELAYED CLOCK OUTPUT (CL ) has

been provided to allow reduced clock drive fan-out and tran-

sition time requirements when cascading packages.

Logic and Connection Diagrams

TL/F/5962–1

Dual-In-Line Package

Order Number CD4031B

TL/F/5962–2

Top View

1995 National Semiconductor Corporation

TL/F/5962

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

中文翻译

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与CD4031BCJ/A+相关器件

型号	品牌	获取价格	描述	数据表
CD4031BCN	NSC	获取价格	IC 4000/14000/40000 SERIES, 64-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTAR
CD4031BCN	TI	获取价格	4000/14000/40000 SERIES, 64-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY O
CD4031BCN/B+	TI	获取价格	IC,SHIFT REGISTER,CMOS,DIP,16PIN,PLASTIC
CD4031BD3	RENESAS	获取价格	Serial In Serial Out, 4000/14000/40000 Series, 64-Bit, Right Direction, Complementary Outp
CD4031BE	ROCHESTER	获取价格	4000/14000/40000 SERIES, 64-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY O
CD4031BE	TI	获取价格	CMOS 64 级静态移位寄存器 \| N \| 16 \| -55 to 125
CD4031BEE4	TI	获取价格	CMOS 64-Stage Static Shift Register 16-PDIP -55 to 125
CD4031BEX	RENESAS	获取价格	Serial In Serial Out, 4000/14000/40000 Series, 64-Bit, Right Direction, Complementary Outp
CD4031BF	RENESAS	获取价格	Serial In Serial Out, 4000/14000/40000 Series, 64-Bit, Right Direction, Complementary Outp
CD4031BF3	RENESAS	获取价格	Serial In Serial Out, 4000/14000/40000 Series, 64-Bit, Right Direction, Complementary Outp

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