Datasheet > CD4029BMS

CD4029BMS

更新时间： 2024-11-11 22:54:19

品牌	Logo	应用领域
英特矽尔 - INTERSIL		计数器逻辑集成电路
页数	文件大小	规格书
11页	127K
描述
CMOS Presettable Up/Down Counter

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CD4029BMS 数据手册

CD4029BMS

CMOS Presettable Up/Down Counter

December 1992

Features

Description

• High-Voltage Type (20V Rating)

CD4029BMS consists of a four-stage binary or BCD-decade up/

• Medium Speed Operation: 8MHz (Typ.) at CL = 50pF down counter with provisions for look-ahead carry in both count-

and VDD - VSS = 10V

ing modes. The inputs consist of a single CLOCK, CARRY-IN

(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET

ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a

CARRY OUT signal are provided as outputs.

• Multi-Package Parallel Clocking for Synchronous High

Speed Output Response or Ripple Clocking for Slow

Clock Input Rise and Fall Times

A high PRESET ENABLE signal allows information on the JAM

INPUTS to preset the counter to any state asynchronously with

the clock. A low on each JAM line, when the PRESET-ENABLE

signal is high, resets the counter to its zero count. The counter is

advanced one count at the positive transition of the clock when

the CARRY-IN and PRE-SET ENABLE signals are low.

Advancement is inhibited when the CARRY-IN or PRESET

ENABLE signals are high. The CARRY-OUT signal is normally

high and goes low when the counter reaches its maximum count

in the UP mode or the minimum count in the DOWN mode pro-

vided the CARRY-IN signal is low. The CARRY-IN signal in the

low state can thus be considered a CLOCK ENABLE. The

CARRY-IN terminal must be connected to VSS when not in use.

• “Preset Enable” and Individual “Jam” Inputs Provided

• Binary or Decade Up/Down Counting

• BCD Outputs in Decade Mode

• 100% Tested for Maximum Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Standardized Symmetrical Output Characteristics

• Maximum Input Current of 1µA at 18V Over Full Pack-

age-Temperature Range; 100nA at 18V and +25^oC

• Noise Margin (Over Full Package Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

Binary counting is accomplished when the BINARY/DECADE

input is high; the counter counts in the decade mode when the

BINARY/DECADE input is low. The counter counts up when the

UP/DOWN input is high, and down when the UP/DOWN input is

low. Multiple packages can be connected in either a parallel-

clocking or a ripple-clocking arrangement as shown in Figure 17.

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Stan-

dards No. 13B, “Standard Speciﬁcations for Descrip-

tion of “B” Series CMOS Device’s

Applications

Parallel clocking provides synchronous control and hence faster

response from all counting outputs. Ripple-clocking allows for

longer clock input rise and fall times.

• Programmable Binary and Decade Counting/Fre-

quency Synthesizers-BCD Output

• Analog to Digital and Digital to Analog Conversion

• Up/Down Binary Counting

The CD4029BMS is supplied in these 16-lead outline packages:

Braze Seal DIP

Frit Seal DIP

H4X

H1F

• Difference Counting

Ceramic Flatpack H6W

• Magnitude and Sign Generation

• Up/Down Decade Counting

Functional Diagram

Pinout

CD4029BMS

TOP VIEW

JAM INPUTS

PRESET

ENABLE

VDD

CARRY IN

(CLOCK

ENABLE)

PRESET ENABLE

16 VDD

4 12 13 3

15 CLOCK

14 Q3

JAM 4

BINARY/

DECADE

JAM 1

13 JAM 3

12 JAM 2

11 Q2

CARRY IN

BUFFERED

OUTPUTS

UP/DOWN 10

10 UP/DOWN

CARRY OUT

VSS

BINARY/DECADE

CLOCK

CARRY

OUT

VSS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3304

7-798

12 3 4 5 6 7...11

中文翻译

下载PDF

与CD4029BMS相关器件

型号	品牌	获取价格	描述	数据表
CD4029BMT	TI	获取价格	CMOS Presettable Up/Down Counter 16-SOIC -55 to 125
CD4029BMTE4	TI	获取价格	CMOS Presettable Up/Down Counter 16-SOIC -55 to 125
CD4029BMTG4	TI	获取价格	4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, P
CD4029BMW	ETC	获取价格	Synchronous Up/Down Counter
CD4029BMW/883	ETC	获取价格	Synchronous Up/Down Counter
CD4029BMW/883C	TI	获取价格	IC,COUNTER,UP/DOWN,4-BIT BIN/DECADE,CMOS,FP,16PIN,CERAMIC
CD4029BNSR	TI	获取价格	CMOS PRESETTABLE UP/DOWN COUNTER
CD4029BNSRE4	TI	获取价格	CMOS Presettable Up/Down Counter 16-SO -55 to 125
CD4029BNSRG4	TI	获取价格	4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, P
CD4029BPWR	TI	获取价格	CMOS PRESETTABLE UP/DOWN COUNTER

与CD4029BMS相关文章

国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

23
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

8
AMD宣布全球裁员约1000人，调整战略聚焦增长
2024-11-14

8
英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

32

产品中心

服务支持

精选活动

关于我们

帮助中心

CD4029BMS

CD4029BMS 数据手册

与CD4029BMS相关器件

与CD4029BMS相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CD4029BMS

CD4029BMS 数据手册

与CD4029BMS相关器件

与CD4029BMS相关文章

您还可以找

您在本页遇到什么问题？