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CD4029BMS

更新时间： 2024-11-13 14:58:23
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
11页 431K
描述
CMOS Presettable Up/Down Counter

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中文翻译

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CD4029BMS 技术参数

生命周期：Transferred包装说明：,
Reach Compliance Code：compliant风险等级：5.57
Is Samacsys：N逻辑集成电路类型：BINARY COUNTER
Base Number Matches：1

CD4029BMS 数据手册

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DATASHEET  
CD4029BMS  
CMOS Presettable Up/Down Counter  
FN3304  
Rev 0.00  
December 1992  
Features  
Description  
• High-Voltage Type (20V Rating)  
CD4029BMS consists of a four-stage binary or BCD-decade up/  
• Medium Speed Operation: 8MHz (Typ.) at CL = 50pF down counter with provisions for look-ahead carry in both count-  
and VDD - VSS = 10V  
ing modes. The inputs consist of a single CLOCK, CARRY-IN  
(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET  
ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a  
CARRY OUT signal are provided as outputs.  
• Multi-Package Parallel Clocking for Synchronous High  
Speed Output Response or Ripple Clocking for Slow  
Clock Input Rise and Fall Times  
A high PRESET ENABLE signal allows information on the JAM  
INPUTS to preset the counter to any state asynchronously with  
the clock. A low on each JAM line, when the PRESET-ENABLE  
signal is high, resets the counter to its zero count. The counter is  
advanced one count at the positive transition of the clock when  
the CARRY-IN and PRE-SET ENABLE signals are low.  
Advancement is inhibited when the CARRY-IN or PRESET  
ENABLE signals are high. The CARRY-OUT signal is normally  
high and goes low when the counter reaches its maximum count  
in the UP mode or the minimum count in the DOWN mode pro-  
vided the CARRY-IN signal is low. The CARRY-IN signal in the  
low state can thus be considered a CLOCK ENABLE. The  
CARRY-IN terminal must be connected to VSS when not in use.  
• “Preset Enable” and Individual “Jam” Inputs Provided  
• Binary or Decade Up/Down Counting  
• BCD Outputs in Decade Mode  
• 100% Tested for Maximum Quiescent Current at 20V  
• 5V, 10V and 15V Parametric Ratings  
• Standardized Symmetrical Output Characteristics  
• Maximum Input Current of 1A at 18V Over Full Pack-  
age-Temperature Range; 100nA at 18V and +25oC  
• Noise Margin (Over Full Package Temperature Range):  
- 1V at VDD = 5V  
- 2V at VDD = 10V  
Binary counting is accomplished when the BINARY/DECADE  
input is high; the counter counts in the decade mode when the  
BINARY/DECADE input is low. The counter counts up when the  
UP/DOWN input is high, and down when the UP/DOWN input is  
low. Multiple packages can be connected in either a parallel-  
clocking or a ripple-clocking arrangement as shown in Figure 17.  
- 2.5V at VDD = 15V  
• Meets All Requirements of JEDEC Tentative Standards  
No. 13B, “Standard Specifications for Description of  
“B” Series CMOS Device’s  
Applications  
Parallel clocking provides synchronous control and hence faster  
response from all counting outputs. Ripple-clocking allows for  
longer clock input rise and fall times.  
• Programmable Binary and Decade Counting/Fre-  
quency Synthesizers-BCD Output  
• Analog to Digital and Digital to Analog Conversion  
• Up/Down Binary Counting  
The CD4029BMS is supplied in these 16-lead outline packages:  
Braze Seal DIP  
Frit Seal DIP  
H4X  
H1F  
• Difference Counting  
Ceramic Flatpack H6W  
• Magnitude and Sign Generation  
• Up/Down Decade Counting  
Functional Diagram  
Pinout  
CD4029BMS  
TOP VIEW  
JAM INPUTS  
PRESET  
ENABLE  
VDD  
16  
1
2
3
4
CARRY IN  
(CLOCK  
ENABLE)  
PRESET ENABLE  
Q4  
1
2
3
4
5
6
7
8
16 VDD  
1
4 12 13 3  
Q1  
6
5
9
15 CLOCK  
14 Q3  
JAM 4  
Q2  
Q3  
Q4  
BINARY/  
DECADE  
11  
JAM 1  
13 JAM 3  
12 JAM 2  
11 Q2  
CARRY IN  
Q1  
BUFFERED  
OUTPUTS  
14  
UP/DOWN 10  
10 UP/DOWN  
CARRY OUT  
VSS  
2
7
9
BINARY/DECADE  
CLOCK  
15  
CARRY  
OUT  
8
VSS  
FN3304 Rev 0.00  
December 1992  
Page 1 of 11  
1234567...11

中文翻译

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