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CD4027BKMSR PDF预览

CD4027BKMSR

更新时间: 2024-11-04 19:58:11
品牌 Logo 应用领域
瑞萨 - RENESAS 输出元件逻辑集成电路触发器
页数 文件大小 规格书
8页 71K
描述
4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16, CERAMIC, DFP-16

CD4027BKMSR 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Transferred零件包装代码:DFP
包装说明:DFP, FL16,.3针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.31Is Samacsys:N
系列:4000/14000/40000JESD-30 代码:R-CDFP-F16
JESD-609代码:e3负载电容(CL):50 pF
逻辑集成电路类型:J-K FLIP-FLOP最大频率@ Nom-Sup:3500000 Hz
最大I(ol):0.00036 A位数:2
功能数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DFP封装等效代码:FL16,.3
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):NOT APPLICABLE电源:5/15 V
Prop。Delay @ Nom-Sup:405 ns传播延迟(tpd):405 ns
认证状态:Not Qualified筛选级别:MIL-PRF-38535 Class V
座面最大高度:2.92 mm子类别:FF/Latches
最大供电电压 (Vsup):18 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:MATTE TIN端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT APPLICABLE总剂量:100k Rad(Si) V
触发器类型:POSITIVE EDGE宽度:6.73 mm
最小 fmax:3.5 MHzBase Number Matches:1

CD4027BKMSR 数据手册

 浏览型号CD4027BKMSR的Datasheet PDF文件第2页浏览型号CD4027BKMSR的Datasheet PDF文件第3页浏览型号CD4027BKMSR的Datasheet PDF文件第4页浏览型号CD4027BKMSR的Datasheet PDF文件第5页浏览型号CD4027BKMSR的Datasheet PDF文件第6页浏览型号CD4027BKMSR的Datasheet PDF文件第7页 
CD4027BMS  
CMOS Dual J-K  
Master-Slave Flip-Flop  
December 1992  
Features  
Pinout  
CD4027BMS  
TOP VIEW  
• High Voltage Type (20V Rating)  
• Set - Reset Capability  
• Static Flip-Flop Operation - Retains State Indefinitely  
with Clock Level Either “High” or “Low”  
Q2  
Q2  
1
2
3
4
5
6
7
8
16 VDD  
15 Q1  
• Medium Speed Operation - 16MHz (typ.) Clock Toggle  
Rate at 10V  
CLOCK 2  
RESET 2  
K2  
14 Q1  
13 CLOCK 1  
12 RESET 1  
11 K1  
• Standardized Symmetrical Output Characteristics  
• 100% Tested For Quiescent Current at 20V  
J2  
10 J1  
SET 2  
VSS  
• Maximum Input Current of 1µA at 18V Over Full  
Package-Temperature Range;  
9
SET 1  
- 100nA at 18V and +25oC  
• Noise Margin (Over Full Package Temperature Range):  
- 1V at VDD = 5V  
- 2V at VDD = 10V  
Functional Diagram  
- 2.5V at VDD = 15V  
VDD  
16  
• 5V, 10V and 15V Parametric Ratings  
SET 1  
9
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
J1 10  
K1 11  
Q1  
15  
F/F1  
CLOCK1 13  
14 Q1  
Applications  
RESET1 12  
• Registers, Counters, Control Circuits  
SET2  
7
J2  
6
1
2
Q2  
Q2  
Description  
K2  
5
3
F/F2  
CD4027BMS is a single monolithic chip integrated circuit con-  
taining two identical complementary-symmetry J-K master-  
slave flip-flops. Each flip-flop has provisions for individual J, K,  
Set Reset, and Clock input signals. Buffered Q and Q signals  
are provided as outputs. This input-output arrangement pro-  
vides for compatible operation with the Intersil CD4013B dual D  
type flip-flop.  
CLOCK2  
4
8
RESET 2  
VSS  
The CD4027BMS is useful in performing control, register, and  
toggle functions. Logic levels present at the J and K inputs  
along with internal self-steering control the state of each flip-  
flop; changes in the flip-flop state are synchronous with the pos-  
itive-going transition of the clock pulse. Set and reset functions  
are independent of the clock and are initiated when a high level  
signal is present at either the Set or Reset input.  
The CD4027BMS is supplied in these 16-lead outline pack-  
ages:  
Braze Seal DIP  
Frit Seal DIP  
H4T  
H1E  
Ceramic Flatpack H6W  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3302  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-780  

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