Datasheet > CD4027BMS

CD4027BMS

更新时间： 2024-11-12 14:58:15

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
8页	333K
描述
CMOS Dual J-K Master-Slave Flip-Flop

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CD4027BMS 技术参数

生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.57
Is Samacsys：	N	逻辑集成电路类型：	J-K FLIP-FLOP
Base Number Matches：	1

CD4027BMS 数据手册

DATASHEET

CD4027BMS

CMOS Dual J-KMaster-Slave Flip-Flop

FN3302

Rev 0.00

December 1992

Features

Pinout

CD4027BMS

TOP VIEW

• High Voltage Type (20V Rating)

• Set - Reset Capability

• Static Flip-Flop Operation - Retains State Indefinitely

with Clock Level Either “High” or “Low”

16 VDD

15 Q1

• Medium Speed Operation - 16MHz (typ.) Clock Toggle

Rate at 10V

CLOCK 2

RESET 2

14 Q1

13 CLOCK 1

12 RESET 1

11 K1

• Standardized Symmetrical Output Characteristics

• 100% Tested For Quiescent Current at 20V

10 J1

SET 2

VSS

• Maximum Input Current of 1A at 18V Over Full

Package-Temperature Range;

- 100nA at 18V and +25^oC

SET 1

• Noise Margin (Over Full Package Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

Functional Diagram

- 2.5V at VDD = 15V

VDD

• 5V, 10V and 15V Parametric Ratings

SET 1

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

J1 10

K1 11

F/F1

CLOCK1 13

14 Q1

Applications

RESET1 12

• Registers, Counters, Control Circuits

SET2

Description

F/F2

CD4027BMS is a single monolithic chip integrated circuit con-

taining two identical complementary-symmetry J-K master-

slave flip-flops. Each flip-flop has provisions for individual J, K,

Set Reset, and Clock input signals. Buffered Q and Q signals

are provided as outputs. This input-output arrangement pro-

vides for compatible operation with the Intersil CD4013B dual D

type flip-flop.

CLOCK2

RESET 2

VSS

The CD4027BMS is useful in performing control, register, and

toggle functions. Logic levels present at the J and K inputs

along with internal self-steering control the state of each flip-

flop; changes in the flip-flop state are synchronous with the pos-

itive-going transition of the clock pulse. Set and reset functions

are independent of the clock and are initiated when a high level

signal is present at either the Set or Reset input.

The CD4027BMS is supplied in these 16-lead outline pack-

ages:

Braze Seal DIP

Frit Seal DIP

H4T

H1E

Ceramic Flatpack H6W

FN3302 Rev 0.00

December 1992

Page 1 of 8

12 3 4 5 6 7 8

中文翻译

下载PDF

与CD4027BMS相关器件

型号	品牌	获取价格	描述	数据表
CD4027BMT	TI	获取价格	CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP
CD4027BMTE4	TI	获取价格	CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP
CD4027BMTG4	TI	获取价格	CMOS Dual J-K Master-Slave Flip-Flop
CD4027BMW	TI	获取价格	4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT,
CD4027BMW/883B	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,CMOS,FP,16PIN,CERAMIC
CD4027BMW/883C	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,CMOS,FP,16PIN,CERAMIC
CD4027BMW-MIL	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,CMOS,FP,16PIN,CERAMIC
CD4027BNSR	TI	获取价格	CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP
CD4027BNSRE4	TI	获取价格	CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP
CD4027BNSRG4	TI	获取价格	CMOS Dual J-K Master-Slave Flip-Flop

与CD4027BMS相关文章

国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

23
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

7
AMD宣布全球裁员约1000人，调整战略聚焦增长
2024-11-14

8
英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

31

产品中心

服务支持

精选活动

关于我们

帮助中心

CD4027BMS

CD4027BMS 技术参数

CD4027BMS 数据手册

与CD4027BMS相关器件

与CD4027BMS相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CD4027BMS

CD4027BMS 技术参数

CD4027BMS 数据手册

与CD4027BMS相关器件

与CD4027BMS相关文章

您还可以找

您在本页遇到什么问题？