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CD4023B PDF预览

CD4023B

更新时间: 2024-01-20 18:06:20
品牌 Logo 应用领域
英特矽尔 - INTERSIL
页数 文件大小 规格书
9页 112K
描述
CMOS NAND Gates

CD4023B 技术参数

生命周期:Transferred包装说明:,
Reach Compliance Code:unknown风险等级:5.78
Base Number Matches:1

CD4023B 数据手册

 浏览型号CD4023B的Datasheet PDF文件第2页浏览型号CD4023B的Datasheet PDF文件第3页浏览型号CD4023B的Datasheet PDF文件第4页浏览型号CD4023B的Datasheet PDF文件第5页浏览型号CD4023B的Datasheet PDF文件第6页浏览型号CD4023B的Datasheet PDF文件第7页 
CD4011BMS, CD4012BMS  
CD4023BMS  
CMOS NAND Gates  
November 1994  
Features  
Pinouts  
CD4011BMS  
TOP VIEW  
• High-Voltage Types (20V Rating)  
• Propagation Delay Time = 60ns (typ.) at CL = 50pF,  
VDD = 10V  
A
B
1
2
3
4
5
6
7
14 VDD  
• Buffered Inputs and Outputs  
13  
12  
H
G
• Standardized Symmetrical Output Characteristics  
J = AB  
K = CD  
C
• Maximum Input Current of 1µA at 18V Over Full Package-  
11 M = GH  
10 L = EF  
Temperature Range; 100nA at 18V and +25oC  
• 100% Tested for Maximum Quiescent Current at 20V  
• 5V, 10V and 15V Parametric Ratings  
D
9
8
E
F
VSS  
• Noise Margin (Over Full Package Temperature Range):  
- 1V at VDD = 5V  
CD4012BMS  
TOP VIEW  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
• Meets All Requirements of JEDEC Tentative Stan-  
dards No. 13B, “Standard Specifications for Descrip-  
tion of “B” Series CMOS Device’s  
J = ABCD  
1
2
3
4
5
6
7
14 VDD  
A
B
13 K = EFGH  
12  
11  
10  
9
H
Description  
C
G
F
CD4011BMS - Quad 2 Input  
CD4012BMS - Dual 4 Input  
CD4023BMS - Triple 3 Input  
D
NC  
VSS  
E
8
NC  
NC = NO CONNECTION  
CD4011BMS, CD4012BMS, and CD4023BMS NAND gates  
provide the system designer with direct implementation of  
the NAND function and supplement the existing family of  
CMOS gates. All inputs and outputs are buffered.  
CD4023BMS  
TOP VIEW  
The CD4011BMS, CD4012BMS and the CD4023BMS is  
supplied in these 14 lead outline packages:  
A
1
2
3
4
5
6
7
14 VDD  
B
13  
12  
11  
G
H
I
CD4011B  
H4Q  
CD4012B  
H4H  
CD4023B  
H4Q  
D
Braze Seal DIP  
Frit Seal DIP  
E
F
H1B  
H1B  
H1B  
10 L = GHI  
H3W  
H3W  
H3W  
K = DEF  
VSS  
9
8
J = ABC  
C
Ceramic Flatpack  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3079  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-53  

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