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CD4023BCN PDF预览

CD4023BCN

更新时间: 2024-11-29 22:33:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 71K
描述
Buffered Triple 3-Input NAND Gate

CD4023BCN 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:0.300 INCH, PLASTIC, MS-001, DIP-14
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.02
Is Samacsys:N系列:4000/14000/40000
JESD-30 代码:R-PDIP-T14长度:19.18 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.00036 A功能数量:3
输入次数:3端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5/15 VProp。Delay @ Nom-Sup:250 ns
传播延迟(tpd):250 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

CD4023BCN 数据手册

 浏览型号CD4023BCN的Datasheet PDF文件第2页浏览型号CD4023BCN的Datasheet PDF文件第3页浏览型号CD4023BCN的Datasheet PDF文件第4页浏览型号CD4023BCN的Datasheet PDF文件第5页浏览型号CD4023BCN的Datasheet PDF文件第6页 
October 1987  
Revised August 2000  
CD4023BC  
Buffered Triple 3-Input NAND Gate  
General Description  
Features  
These triple gates are monolithic complementary MOS  
(CMOS) integrated circuits constructed with N- and P-  
channel enhancement mode transistors. They have equal  
source and sink current capabilities and conform to stan-  
dard B series output drive. The devices also have buffered  
outputs which improve transfer characteristics by providing  
very high gain. All inputs are protected against static dis-  
Wide supply voltage range: 3.0V to 15V  
High noise immunity: 0.45 VDD (typ)  
Low power TTL compatibility:  
fan out of 2 driving 74L or 1 driving 74LS  
5V–10V–15V parametric ratings  
Symmetrical output characteristics  
charge with diodes to VDD and VSS  
.
Maximum input leakage 1 µA at 15V over full  
temperature range  
Ordering Code:  
Order Number Package Number  
Package Description  
CD4023BCM  
CD4023BCS  
CD4023BCN  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xtot he ordering code.  
Connection Diagram  
Block Diagram  
1
/
3 Device Shown  
*All Inputs Protected by Standard CMOS Input Protection Circuit.  
Top View  
© 2000 Fairchild Semiconductor Corporation  
DS005956  
www.fairchildsemi.com  

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