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CD4023BCS PDF预览

CD4023BCS

更新时间: 2024-01-13 00:02:01
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 逻辑集成电路光电二极管
页数 文件大小 规格书
6页 71K
描述
Buffered Triple 3-Input NAND Gate

CD4023BCS 数据手册

 浏览型号CD4023BCS的Datasheet PDF文件第2页浏览型号CD4023BCS的Datasheet PDF文件第3页浏览型号CD4023BCS的Datasheet PDF文件第4页浏览型号CD4023BCS的Datasheet PDF文件第5页浏览型号CD4023BCS的Datasheet PDF文件第6页 
October 1987  
Revised August 2000  
CD4023BC  
Buffered Triple 3-Input NAND Gate  
General Description  
Features  
These triple gates are monolithic complementary MOS  
(CMOS) integrated circuits constructed with N- and P-  
channel enhancement mode transistors. They have equal  
source and sink current capabilities and conform to stan-  
dard B series output drive. The devices also have buffered  
outputs which improve transfer characteristics by providing  
very high gain. All inputs are protected against static dis-  
Wide supply voltage range: 3.0V to 15V  
High noise immunity: 0.45 VDD (typ)  
Low power TTL compatibility:  
fan out of 2 driving 74L or 1 driving 74LS  
5V–10V–15V parametric ratings  
Symmetrical output characteristics  
charge with diodes to VDD and VSS  
.
Maximum input leakage 1 µA at 15V over full  
temperature range  
Ordering Code:  
Order Number Package Number  
Package Description  
CD4023BCM  
CD4023BCS  
CD4023BCN  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xtot he ordering code.  
Connection Diagram  
Block Diagram  
1
/
3 Device Shown  
*All Inputs Protected by Standard CMOS Input Protection Circuit.  
Top View  
© 2000 Fairchild Semiconductor Corporation  
DS005956  
www.fairchildsemi.com  

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