The MC14016B quad bilateral switch is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Each MC14016B consists of four independent
switches capable of controlling either digital or analog signals. The
quad bilateral switch is used in signal gating, chopper, modulator,
demodulator and CMOS logic implementation.
http://onsemi.com
MARKING
DIAGRAMS
14
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Linearized Transfer Characteristics
PDIP–14
P SUFFIX
CASE 646
MC14016BCP
AWLYYWW
• Low Noise — 12 nV/√Cycle, f ≥ 1.0 kHz typical
1
• Pin–for–Pin Replacements for CD4016B, CD4066B (Note improved
transfer characteristic design causes more parasitic coupling
capacitance than CD4016)
14
SOIC–14
D SUFFIX
CASE 751A
14016B
AWLYWW
• For Lower R , Use The HC4016 High–Speed CMOS Device or
ON
The MC14066B
1
• This Device Has Inputs and Outputs Which Do Not Have ESD
Protection. Antistatic Precautions Must Be Taken.
14
SOEIAJ–14
F SUFFIX
CASE 965
MC14016B
AWLYWW
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
SS
1
Symbol
Parameter
Value
Unit
V
A
= Assembly Location
V
DD
DC Supply Voltage Range
–0.5 to +18.0
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
V , V
in out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
DD
I
in
Input Current (DC or Transient)
per Control Pin
±10
mA
ORDERING INFORMATION
I
Switch Through Current
±25
mA
SW
Device
Package
PDIP–14
SOIC–14
Shipping
P
Power Dissipation,
per Package (Note 3.)
500
mW
D
MC14016BCP
MC14016BD
2000/Box
55/Rail
T
A
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
T
stg
MC14016BDR2
MC14016BF
SOIC–14 2500/Tape & Reel
T
Lead Temperature
(8–Second Soldering)
L
See Note 1.
See Note 1.
SOEIAJ–14
SOEIAJ–14
MC14016BFEL
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14016B/D