Datasheet > CD4015BMS

CD4015BMS

更新时间： 2024-11-14 20:22:39

品牌	Logo	应用领域
瑞萨 - RENESAS		逻辑集成电路
页数	文件大小	规格书
8页	117K
描述
Serial In Parallel Out

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中文翻译

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技术参数
数据手册

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CD4015BMS 技术参数

生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.56
Is Samacsys：	N	逻辑集成电路类型：	SERIAL IN PARALLEL OUT
Base Number Matches：	1

CD4015BMS 数据手册

CD4015BMS

CMOS Dual 4-Stage Static Shift Register

With Serial Input/Parallel Output

December 1992

Features

Pinout

CD4015BMS

TOP VIEW

• High-Voltage Type (20V Rating)

• Medium Speed Operation 12MHz (typ.) Clock Rate at

VDD - VSS = 10V

CLOCK B

Q4B

16 VDD

• Fully Static Operation

15 DATA B

14 RESET B

13 Q1B

Q3A

• 8 Master-Slave Flip-Flops Plus Input and Output Buffering

• 100% Tested For Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

Q2A

Q1A

12 Q2B

RESET A

DATA A

VSS

11 Q3B

• Standardized Symmetrical Output Characteristics

10 Q4A

• Maximum Input Current of 1µA at 18V Over Full Pack-

CLOCK A

age-Temperature Range; 100nA at 18V and 25^oC

• Noise Margin (Full Package-Temperature Range) =

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

Functional Diagram

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

VDD

DATA A

Q1A

Q2A

Q3A

Q4A

Applications

CLOCK A

• Serial-Input/Parallel-Output Data Queueing

• Serial to Parallel Data Conversion

• General-Purpose Register

STAGE

RESET A

DATA B

Q1B

Q2B

Q3B

Q4B

Description

CLOCK B

STAGE

CD4015BMS consists of two identical, independent, 4-stage

serial-input/parallel output registers. Each register has inde-

pendent CLOCK and RESET inputs as well as a single serial

DATA input. “Q” outputs are available from each of the four

stages on both registers. All register stages are D type, mas-

ter-slave ﬂip-ﬂops. The logic level present at the DATA input

is transferred into the ﬁrst register stage and shifted over one

stage at each positive-going clock transition. Resetting of all

stages is accomplished by a high level on the reset line.

package, or to more than 8 stages using additional

CD4015BMS’s is possible.

RESET B

VSS

The CD4015BMS is supplied in these 16 lead outline pack-

ages:

Braze Seal DIP

Frit Seal DIP

H4X

H1F

Ceramic Flatpack H6W

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3295

7-89

12 3 4 5 6 7 8

中文翻译

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与CD4015BMS相关器件

型号	品牌	获取价格	描述	数据表
CD4015BMT	TI	获取价格	CMOS Dual 4-Stage Static Shift Register
CD4015BMTE4	TI	获取价格	4000/14000/40000 SERIES, 4-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, P
CD4015BMTE4	ROCHESTER	获取价格	Serial In Parallel Out, 4000/14000/40000 Series, 4-Bit, Right Direction, True Output, CMOS
CD4015BMTG4	ROCHESTER	获取价格	Serial In Parallel Out, 4000/14000/40000 Series, 4-Bit, Right Direction, True Output, CMOS
CD4015BNSR	TI	获取价格	CMOS Dual 4-Stage Static Shift Register
CD4015BNSR	ROCHESTER	获取价格	Serial In Parallel Out, 4000/14000/40000 Series, 4-Bit, Right Direction, True Output, CMOS
CD4015BNSRE4	TI	获取价格	4000/14000/40000 SERIES, 4-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, P
CD4015BNSRG4	TI	获取价格	4000/14000/40000 SERIES, 4-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, P
CD4015BNSRG4	ROCHESTER	获取价格	Serial In Parallel Out, 4000/14000/40000 Series, 4-Bit, Right Direction, True Output, CMOS
CD4015BPW	TI	获取价格	CMOS Dual 4-Stage Static Shift Register

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