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CD4011BCNX PDF预览

CD4011BCNX

更新时间: 2024-11-17 21:53:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
9页 120K
描述
Quad 2-Input NOR Buffered B Series Gate . Quad 2-Input NAND Buffered B Series Gate

CD4011BCNX 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.28系列:4000/14000/40000
JESD-30 代码:R-PDIP-T14长度:19.18 mm
逻辑集成电路类型:NAND GATE功能数量:4
输入次数:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
传播延迟(tpd):250 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mm

CD4011BCNX 数据手册

 浏览型号CD4011BCNX的Datasheet PDF文件第2页浏览型号CD4011BCNX的Datasheet PDF文件第3页浏览型号CD4011BCNX的Datasheet PDF文件第4页浏览型号CD4011BCNX的Datasheet PDF文件第5页浏览型号CD4011BCNX的Datasheet PDF文件第6页浏览型号CD4011BCNX的Datasheet PDF文件第7页 
October 1987  
Revised March 2002  
CD4001BC/CD4011BC  
Quad 2-Input NOR Buffered B Series Gate •  
Quad 2-Input NAND Buffered B Series Gate  
General Description  
Features  
Low power TTL:  
The CD4001BC and CD4011BC quad gates are monolithic  
complementary MOS (CMOS) integrated circuits con-  
structed with N- and P-channel enhancement mode tran-  
sistors. They have equal source and sink current  
capabilities and conform to standard B series output drive.  
The devices also have buffered outputs which improve  
transfer characteristics by providing very high gain.  
Fan out of 2 driving 74L compatibility: or 1 driving 74LS  
5V–10V–15V parametric ratings  
Symmetrical output characteristics  
Maximum input leakage 1 µA at 15V over full  
temperature range  
All inputs are protected against static discharge with diodes  
to VDD and VSS  
.
Ordering Code:  
Order Number  
CD4001BCM  
CD4001BCSJ  
CD4001BCN  
CD4011BCM  
CD4011BCN  
Package Number  
Package Description  
M14A  
M14D  
N14A  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Connection Diagrams  
Pin Assignments for DIP, SOIC and SOP  
CD4001BC  
Pin Assignments for DIP and SOIC  
CD4011BC  
Top View  
Top View  
© 2002 Fairchild Semiconductor Corporation  
DS005939  
www.fairchildsemi.com  

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