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CD40100BMS

更新时间： 2024-11-03 22:54:19
品牌 Logo 应用领域
英特矽尔 - INTERSIL 移位寄存器
页数 文件大小 规格书
9页 69K
描述
CMOS 32-Stage Static Left/Right Shift Register

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CD40100BMS 数据手册

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CD40100BMS  
CMOS 32-Stage Static  
Left/Right Shift Register  
December 1992  
Features  
Description  
• High Voltage Type (20V Rating)  
• Fully Static Operation  
CD40100BMS is a 32-Stage shift register containing 32  
D-type master-slave flip-flops.  
The data present at the SHIFT RIGHT INPUT is transferred  
into the first register stage synchronously with the positive  
CLOCK edge, provided the LEFT/RIGHT CONTROL is at a  
low level, the RECIRCULATE CONTROL is at a high level,  
and the CLOCK INHIBIT is low. If the LEFT/RIGHT  
CONTROL is at a high level and the RECIRCULATE  
CONTROL is also high, data at the SHIFT LEFT INPUT is  
transferred into the 32nd register stage synchronously with  
the positive CLOCK transition, provided the CLOCK INHIBIT  
is low. The state of the LEFT/RIGHT CONTROL,  
RECIRCULATE CONTROL, and CLOCK INHIBIT should not  
be changed when the CLOCK is high.  
• Shift Left/Shift Right Capability  
• Multiple Package Cascading  
• Recirculate Capability  
• LIFO of FIFO Capability  
• 100% Tested for Quiescent Current at 20V  
• 5V, 10V and 15V Parametric Ratings  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and +25oC  
• Noise Margin (Over Full Package/Temperature Range)  
- 1V at VDD = 5V  
Data is shifted one stage left or one stage right depending on  
the state of the LEFT/RIGHT CONTROL, synchronously with  
the positive CLOCK edge. Data clocked into the first or 32nd  
register states is available at the SHIFT LEFT or SHIFT  
RIGHT OUTPUT respectively, on the next negative CLOCK  
transition (see Data Transfer Table). No shifting occurs on the  
positive CLOCK edge if the CLOCK INHIBIT line is at a high  
level. With the RECIRCULATE CONTROL low, data in the  
32nd stage is shifted into the first stage when the LEFT/  
RIGHT CONTROL is low and from the first stage to the 32nd  
stage when the LEFT/RIGHT CONTROL is low, and from the  
first state to the 32nd stage when the LEFT/RIGHT control is  
high. The CD40100BMS is supplied in these 16-lead outline  
packages:  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
• Standardized, Symmetrical Output Characteristics  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
Applications  
• Serial Shift Registers  
• Time Delay Circuits  
Braze Seal DIP  
Frit Seal DIP  
Ceramic Flatpack  
H4T  
H2R  
H6W  
• Expandable N-Bit Data Storage Stack (LIFO Operation)  
Functional Diagram  
Pinout  
CD40100BMS  
TOP VIEW  
LEFT/RIGHT  
CONTROL  
NC  
CLOCK INHIBIT  
CLOCK  
1
2
3
4
5
6
7
8
16 VDD  
15 NC  
14 NC  
13  
SHIFT RIGHT  
11  
SHIFT RIGHT  
12  
IN  
OUT  
OUT  
CLOCK  
4
LEFT/RIGHT  
CONTROL  
SHIFT LEFT OUT  
NC  
13  
12 SHIFT RIGHT OUT  
11 SHIFT RIGHT IN  
10 NC  
CLOCK INHIBIT  
2
SHIFT LEFT  
4
SHIFT LEFT IN  
NC  
SHIFT LEFT  
6
IN  
VSS = 8  
VDD = 16  
RECIRCULATE  
CONTROL  
9
VSS  
9
NC = 1, 5, 7, 10, 14, 15  
RECIRCULATE  
CONTROL  
NC = NO CONNECTION  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3349  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
7-1277  
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