Datasheet > CD40101BMS

CD40101BMS

更新时间： 2024-09-29 22:54:19

品牌	Logo	应用领域
英特矽尔 - INTERSIL		/
页数	文件大小	规格书
8页	108K
描述
CMOS 9-Bit Parity Generator/Checker

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中文翻译

获取价格

数据手册

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CD40101BMS 数据手册

CD40101BMS

CMOS 9-Bit Parity Generator/Checker

December 1992

Features

Pinout

CD40101BMS

TOP VIEW

• High Voltage Type (20V Rating)

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

14 VDD

13 D8

12 D7

11 D6

10 D5

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25^oC

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

ODD OUT

VSS

EVEN OUT

- 2.5V at VDD = 15V

INHIBIT

• Standardized Symmetrical Output Characteristics

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

Description

Functional Diagram

The CD40101BMS is a 9-bit (8 data bits plus 1 parity bit)

parity generator/checker. It may be used to detect errors in

data transmission or data retrieval. Odd and even outputs

facilitate odd or even parity generation and checking.

INHIBIT

VDD = 14

VSS = 7

When used as a parity generator, a parity bit is supplied

along with the data to generate an even or odd parity output.

When used as a parity checker, the received data bits and

parity bits are compared for correct parity. The even or odd

outputs are used to indicate an error in the received data.

EVEN

OUTPUT

Word length capability is expandable by cascading. The

CD40101BMS is also provided with an inhibit control. If the

inhibit control is set at logical “1”, the even and odd outputs

go to a logical “0”.

The CD40101BMS is supplied in these 14 lead outline

packages:

D5 10

D6 11

D7 12

D8 13

DECODE

Braze Seal DIP

Frit Seal DIP

H4H

H1B

H3W

ODD

OUTPUT

Ceramic Flatpack

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3350

7-1286

12 3 4 5 6 7 8

中文翻译

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