Datasheet > CD4001BMS

CD4001BMS

更新时间： 2024-11-03 22:54:19

品牌	Logo	应用领域
英特矽尔 - INTERSIL		逻辑集成电路栅
页数	文件大小	规格书
9页	146K
描述
CMOS NOR Gate

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中文翻译

获取价格

数据手册

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CD4001BMS 数据手册

CD4000BMS, CD4001BMS

CD4002BMS, CD4025BMS

CMOS NOR Gate

November 1994

Features

Pinouts

CD4000BMS

TOP VIEW

• High-Voltage Types (20V Rating)

• Propagation Delay Time = 60ns (typ.) at CL = 50pF,

VDD = 10V

14 VDD

• Buffered Inputs and Outputs

• Standard Symmetrical Output Characteristics

• 100% Tested for Maximum Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

H = A + B + C

VSS

10 K = D + E + F

L = G

• Maximum Input Current of 1µA at 18V Over Full Pack-

age-Temperature Range; 100nA at 18V and +25^oC

NC = NO CONNECTION

• Noise Margin (Over Full Package Temperature Range):

- 1V at VDD = 5V

CD4001BMS

TOP VIEW

- 2V at VDD = 10V

14 VDD

- 2.5V at VDD = 15V

J = A + B

K = C + D

• Meets All Requirements of JEDEC Tentative Stan-

dards No. 13B, “Standard Speciﬁcations for Descrip-

tion of “B” Series CMOS Device’s

11 M = G + H

10 L = E + F

Description

CD4000BMS - Dual 3 Plus Inverter

CD4001BMS - Quad 2 Input

CD4002BMS - Dual 4 Input

CD4025BMS - Triple 3 Input

VSS

NC = NO CONNECTION

CD4002BMS

TOP VIEW

CD4000BMS,

CD4001BMS,

CD4002BMS,

and

J = A + B + C + D

14 VDD

CD4025BMS NOR gates provide the system designer with

direct implementation of the NOR function and supplement

the existing family of CMOS gates. All inputs and outputs are

buffered.

13 K = E + F + G + H

The CD4000BMS, CD4001BMS, CD4002BMS and the

CD4025BMS is supplied in these 14 lead outline packages:

VSS

CD4000B CD4001B CD4002B CD4025B

NC = NO CONNECTION

H4X

H1B

H3W

H4Q

H1B

H3W

H4Q

H1B

H3W

H4Q

H1B

H3W

Braze Seal DIP

Frit Seal DIP

CD4025BMS

TOP VIEW

Ceramic Flatpack

14 VDD

K = D + E + F

VSS

10 L = G + H + I

J = A + B + C

NC = NO CONNECTION

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3289

7-649

12 3 4 5 6 7...9

中文翻译

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