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CAT28LV64J-25T PDF预览

CAT28LV64J-25T

更新时间: 2024-11-29 22:16:11
品牌 Logo 应用领域
CATALYST 内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
12页 528K
描述
64K-Bit CMOS PARALLEL EEPROM

CAT28LV64J-25T 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:SOIC包装说明:SOP, SOP28,.4
针数:28Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.55最长访问时间:250 ns
其他特性:100000 PROGRAM/ERASE CYCLES; 100 YEAR DATA RETENTION命令用户界面:NO
数据轮询:YES数据保留时间-最小值:100
耐久性:100000 Write/Erase CyclesJESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:17.9 mm
内存密度:65536 bit内存集成电路类型:EEPROM
内存宽度:8湿度敏感等级:1
功能数量:1端子数量:28
字数:8192 words字数代码:8000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8KX8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP28,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE页面大小:32 words
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:3.3 V编程电压:3 V
认证状态:Not Qualified座面最大高度:2.65 mm
最大待机电流:0.0001 A子类别:EEPROMs
最大压摆率:0.008 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
切换位:YES宽度:7.5 mm
最长写入周期时间 (tWC):5 ms

CAT28LV64J-25T 数据手册

 浏览型号CAT28LV64J-25T的Datasheet PDF文件第2页浏览型号CAT28LV64J-25T的Datasheet PDF文件第3页浏览型号CAT28LV64J-25T的Datasheet PDF文件第4页浏览型号CAT28LV64J-25T的Datasheet PDF文件第5页浏览型号CAT28LV64J-25T的Datasheet PDF文件第6页浏览型号CAT28LV64J-25T的Datasheet PDF文件第7页 
E
CAT28LV64  
64K-Bit CMOS PARALLEL EEPROM  
TM  
FEATURES  
CMOS and TTL compatible I/O  
3.0V to 3.6 V Supply  
Automatic page write operation:  
– 1 to 32 bytes in 5ms  
Read access times:  
– 150/200/250ns  
– Page load timer  
Low power CMOS dissipation:  
– Active: 8 mA max.  
End of write detection:  
– Toggle bit  
– Standby: 100 µA max.  
DATA polling  
Simple write operation:  
Hardware and software write protection  
100,000 program/erase cycles  
100 year data retention  
– On-chip address and data latches  
– Self-timed write cycle with auto-clear  
Fast write cycle time:  
– 5ms max.  
Commercial, industrial and automotive  
temperature ranges  
DESCRIPTION  
The CAT28LV64 is a low voltage, low power, CMOS  
parallel EEPROM organized as 8K x 8-bits. It requires a  
simple interface for in-system programming. On-chip  
addressanddatalatches,self-timedwritecyclewithauto-  
clear and VCC power up/down write protection eliminate  
additional timing and protection hardware. DATA Polling  
and Toggle status bit signal the start and end of the self-  
timed write cycle. Additionally, the CAT28LV64 features  
hardware and software write protection.  
The CAT28LV64 is manufactured using Catalyst’s  
advanced CMOS floating gate technology. It is designed  
to endure 100,000 program/erase cycles and has a data  
retention of 100 years. The device is available in JEDEC  
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32-  
pin PLCC packages.  
BLOCK DIAGRAM  
8,192 x 8  
E2PROM  
ARRAY  
ROW  
ADDR. BUFFER  
A –A  
5
12  
DECODER  
& LATCHES  
INADVERTENT  
WRITE  
HIGH VOLTAGE  
GENERATOR  
32 BYTE PAGE  
REGISTER  
V
CC  
PROTECTION  
CE  
OE  
WE  
CONTROL  
LOGIC  
I/O BUFFERS  
DATA POLLING  
AND  
TIMER  
TOGGLE BIT  
I/O –I/O  
0
7
ADDR. BUFFER  
& LATCHES  
A –A  
COLUMN  
0
4
DECODER  
Doc. No. 1010, Rev. D  
© 2004 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
1

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