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CAT28C512HT14I-12T PDF预览

CAT28C512HT14I-12T

更新时间: 2024-10-27 02:56:55
品牌 Logo 应用领域
CATALYST 可编程只读存储器
页数 文件大小 规格书
10页 101K
描述
512K-Bit CMOS PARALLEL E2PROM

CAT28C512HT14I-12T 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:TSOP包装说明:TSOP1,
针数:40Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.14最长访问时间:120 ns
其他特性:100000 PROGRAM/ERASE CYCLES; DATA RETENTION = 100 YEARS数据保留时间-最小值:100
JESD-30 代码:R-PDSO-G40JESD-609代码:e0
长度:12.4 mm内存密度:524288 bit
内存集成电路类型:EEPROM内存宽度:8
湿度敏感等级:2A功能数量:1
端子数量:40字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:64KX8封装主体材料:PLASTIC/EPOXY
封装代码:TSOP1封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):240编程电压:5 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:10 mm
Base Number Matches:1

CAT28C512HT14I-12T 数据手册

 浏览型号CAT28C512HT14I-12T的Datasheet PDF文件第2页浏览型号CAT28C512HT14I-12T的Datasheet PDF文件第3页浏览型号CAT28C512HT14I-12T的Datasheet PDF文件第4页浏览型号CAT28C512HT14I-12T的Datasheet PDF文件第5页浏览型号CAT28C512HT14I-12T的Datasheet PDF文件第6页浏览型号CAT28C512HT14I-12T的Datasheet PDF文件第7页 
Advanced  
CAT28C512/513  
512K-Bit CMOS PARALLEL E2PROM  
FEATURES  
Fast Read Access Times: 120/150 ns  
Automatic Page Write Operation:  
–1 to 128 Bytes in 5ms  
Low Power CMOS Dissipation:  
–Active: 50 mA Max.  
–Page Load Timer  
–Standby: 200 µA Max.  
End of Write Detection:  
–Toggle Bit  
Simple Write Operation:  
DATA Polling  
–On-Chip Address and Data Latches  
–Self-Timed Write Cycle with Auto-Clear  
Hardware and Software Write Protection  
100,000 Program/Erase Cycles  
100 Year Data Retention  
Fast Write Cycle Time:  
–5ms Max  
CMOS and TTL Compatible I/O  
Commercial, Industrial and Automotive  
Temperature Ranges  
DESCRIPTION  
The CAT28C512/513 is manufactured using Catalyst’s  
advancedCMOSfloatinggatetechnology.Itisdesigned  
to endure 100,000 program/erase cycles and has a data  
retention of 100 years. The device is available in JEDEC  
approved 32-pin DIP, PLCC, 32-pin TSOP and 40-pin  
TSOP packages.  
TheCAT28C512/513isafast,lowpower,5V-onlyCMOS  
parallel E2PROM organized as 64K x 8-bits. It requires  
a simple interface for in-system programming. On-chip  
address and data latches, self-timed write cycle with  
auto-clear and VCC power up/down write protection  
eliminate additional timing and protection hardware.  
DATA Polling and Toggle status bits signal the start and  
end of the self-timed write cycle. Additionally, the  
CAT28C512/513 features hardware and software write  
protection.  
BLOCK DIAGRAM  
65,536 x 8  
E2PROM  
ARRAY  
ROW  
DECODER  
ADDR. BUFFER  
A –A  
7
15  
& LATCHES  
INADVERTENT  
WRITE  
PROTECTION  
HIGH VOLTAGE  
GENERATOR  
128 BYTE PAGE  
REGISTER  
V
CC  
CE  
OE  
WE  
CONTROL  
TIMER  
I/O BUFFERS  
DATA POLLING  
AND  
TOGGLE BIT  
I/O –I/O  
0
7
ADDR. BUFFER  
& LATCHES  
A –A  
COLUMN  
DECODER  
0
6
5096 FHD F02  
© 1998 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 25074-00 2/98  
1

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