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CAT24C512C8ATR PDF预览

CAT24C512C8ATR

更新时间: 2024-11-18 21:17:27
品牌 Logo 应用领域
安森美 - ONSEMI 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟内存集成电路
页数 文件大小 规格书
17页 133K
描述
I2C/2-WIRE SERIAL EEPROM

CAT24C512C8ATR 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:WLCSP-8Reach Compliance Code:compliant
风险等级:5.75最大时钟频率 (fCLK):0.4 MHz
JESD-30 代码:R-PBGA-B8长度:1.65 mm
内存密度:524288 bit内存集成电路类型:EEPROM
内存宽度:8功能数量:1
端子数量:8字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:64KX8封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行:SERIAL
峰值回流温度(摄氏度):NOT SPECIFIED座面最大高度:0.6 mm
串行总线类型:I2C最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.8 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1.39 mm
最长写入周期时间 (tWC):5 msBase Number Matches:1

CAT24C512C8ATR 数据手册

 浏览型号CAT24C512C8ATR的Datasheet PDF文件第2页浏览型号CAT24C512C8ATR的Datasheet PDF文件第3页浏览型号CAT24C512C8ATR的Datasheet PDF文件第4页浏览型号CAT24C512C8ATR的Datasheet PDF文件第5页浏览型号CAT24C512C8ATR的Datasheet PDF文件第6页浏览型号CAT24C512C8ATR的Datasheet PDF文件第7页 
CAT24C512  
512 Kb I2C CMOS Serial  
EEPROM  
Description  
The CAT24C512 is a 512 Kb Serial CMOS EEPROM, internally  
organized as 65,536 words of 8 bits each.  
www.onsemi.com  
It features a 128−byte page write buffer and supports the Standard  
2
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I C protocol.  
Write operations can be inhibited by taking the WP pin High (this  
protects the entire memory).  
External address pins make it possible to address up to eight  
CAT24C512 devices on the same bus.  
On−Chip ECC (Error Correction Code) makes the device suitable  
for high reliability applications.  
UDFN−8  
HU5 SUFFIX  
CASE 517BU  
TSSOP−8  
Y SUFFIX  
CASE 948AL  
SOIC−8  
X SUFFIX  
CASE 751BE  
SOIC−8  
W SUFFIX  
CASE 751BD  
Features  
2
Supports Standard, Fast and Fast−Plus I C Protocol  
PDIP−8  
L SUFFIX  
CASE 646AA  
MSOP−8  
Z SUFFIX  
CASE 846AD  
1.8 V to 5.5 V Supply Voltage Range  
128−Byte Page Write Buffer  
WLCSP−8*  
C8A SUFFIX  
CASE 567JL  
Hardware Write Protection for Entire Memory  
* Preliminary. Please contact factory.  
2
Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs  
(SCL and SDA)  
PIN CONFIGURATIONS  
Low Power CMOS Technology  
1,000,000 Program/Erase Cycles  
100 Year Data Retention  
Pin A1  
Reference  
A
0
A
1
A
2
V
CC  
1
WP  
SCL  
SDA  
Industrial and Extended Temperature Range  
SDA  
VCC  
WP  
V
SS  
8−pin PDIP, SOIC, TSSOP, MSOP, 8−pad UDFN and 8−ball WLCSP  
SCL  
Packages  
A
2
PDIP (L), SOIC (W, X),  
TSSOP (Y), MSOP (Z)  
UDFN (HU5)  
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS  
A
1
Compliant  
A
0
VSS  
(Top View)  
V
CC  
For the location of  
Pin 1, please consult  
the corresponding  
package drawing.  
WLCSP (C8A)  
(Top View)  
SCL  
PIN FUNCTION  
CAT24C512  
SDA  
A , A , A  
2
1
0
Pin Name  
Function  
Device Address  
WP  
A , A , A  
0
1
2
SDA  
Serial Data  
Serial Clock  
Write Protect  
Power Supply  
Ground  
SCL  
WP  
V
SS  
Figure 1. Functional Symbol  
V
CC  
V
SS  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 17 of this data sheet.  
© Semiconductor Components Industries, LLC, 2015  
1
Publication Order Number:  
June, 2015 − Rev. 7  
CAT24C512/D  

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