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C9827JT PDF预览

C9827JT

更新时间: 2024-10-27 23:39:19
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其他 - ETC 晶体时钟发生器外围集成电路光电二极管
页数 文件大小 规格书
25页 171K
描述
CPU SYSTEM CLOCK GENERATOR|TSSOP|56PIN|PLASTIC

C9827JT 数据手册

 浏览型号C9827JT的Datasheet PDF文件第6页浏览型号C9827JT的Datasheet PDF文件第7页浏览型号C9827JT的Datasheet PDF文件第8页浏览型号C9827JT的Datasheet PDF文件第10页浏览型号C9827JT的Datasheet PDF文件第11页浏览型号C9827JT的Datasheet PDF文件第12页 
C9827J  
High Performance Pentium® 4 Clock Synthesizer  
AC Parameters (Cont.)  
66 MHz  
100 MHz  
133 MHz  
200 MHz  
Symbol  
Parameter  
Units  
Notes  
Min  
Max  
55  
71.0  
4.0  
Min  
Max  
55  
71.0  
4.0  
Min  
Max  
55  
71.0  
4.0  
Min  
Max  
55  
71.0  
4.0  
TDC  
TPeriod  
Tr / Tf  
REF Duty Cycle  
REF period  
REF rise and fall  
times  
45  
69.8413  
1.0  
45  
69.8413  
1.0  
45  
69.8413  
1.0  
45  
69.8413  
1.0  
%
nS  
nS  
2, 4  
2, 4  
2, 3  
TCCJ  
REF Cycle to  
Cycle Jitter  
-
1000  
-
1000  
-
1000  
-
1000  
pS  
2, 4  
tpZL, tpZH  
tpLZ, tpZH  
tstable  
Output enable  
delay (all outputs)  
Output disable  
delay (all outputs)  
All clock  
1.0  
1.0  
-
10.0  
10.0  
3
1.0  
1.0  
-
10.0  
10.0  
3
1.0  
1.0  
-
10.0  
10.0  
3
1.0  
1.0  
-
10.0  
10.0  
3
nS  
nS  
11  
11  
11  
mS  
Stabilization from  
power-up  
tss  
tsh  
tsu  
Stopclock Set Up  
Time  
Stopclock Hold  
Time  
Oscillator startup  
time  
10.0  
-
-
10.0  
-
-
10.0  
-
-
10.0  
-
-
nS  
nS  
10  
10  
12  
0
-
0
-
0
-
0
-
X
X
X
X
mS  
(VDD = VDDA = 3.3V ±5%, TA = 0°C to +70°C)  
Note 1: This parameter is measured as an average over 1uS duration, with a crystal center frequency of 14.31818MHz  
Note 2: All outputs loaded as per table 5 below.  
Note 3: Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals (see test and measurement setup  
section of this data sheet)  
Note 4: Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals (see test and measurement setup section of this  
data sheet).  
Note 5: This measurement is applicable with Spread ON or Spread OFF.  
Note 6: Measured from Vol = 0.175V to Voh = 0.525V.  
Note 7: Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86V. Rise/fall time matching is defined as “the  
instantaneous difference between maximum clk rise (fall) and minimum clk# fall (rise) time, or minimum clk rise (fall) and maximum clk# fall  
(rise) time”. This parameter is designed form waveform symmetry.  
Note 8: The time specified is measured from when all VDD’s reach their supply rail (3.3V) till the frequency output is stable and operating within the  
specifications.  
Note 9: Measured from when both SEL1 and SEL0 are low  
Note 10: CPU_STP# and PCI_STP# setup time with respect to any PCI_F clock to guarantee that the effected clock will stop or start at the next  
PCI_F clock’s rising edge.  
Note 11: When Xin is driven from an external clock source.  
Note 12: When Crystal meets minimum 40 ohm device series resistance specification.  
Note 13: Measured between 0.2Vdd and .7Vdd  
Note 14: This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70  
but the REF clock duty cycle will not be within data sheet specifications.  
Note 15: Vpullup(external)=1.5V, Min=(Vpullup(external)/2)-150mV, Max=(Vpullup(external)/2)+150mV  
Note 16: Vp = V pull-up (external), Vdif specifies the minimum input differential voltage (Vtr-Vcp) required for switching, where Vtr is the true input  
level and Vcp os the compliment input level.  
Note 17: Measured at crossing point (Vx) or where subtraction of CLK-CLK# crosses 0 volts.  
Note 18: This figure is additive to any jitter already present when the 66IN pin is being used as an input. Otherwise a 500 ps jitter figure is specified.  
Note 19: THIGH is measured at 2.4V for non host outputs.  
Note 20: TLOW is measured at 0.4V for all outputs.  
Note 21: Determined as a fraction of 2*(Trise-Tfall)/ (Trise+Tfall).  
Note 22: Test load is Rta=33.2 ohms, Rd=49.9 ohms.  
Note 23: These crossing points refer to only crossing points containing a rising edge of a Host output.  
Note 24: This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.  
Note 25: Measurement taken from differential waveform, from –0.35V to +0.35V.  
Note 26: Measured in absolute voltage, i.e. single-ended measurement.  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07107 Rev. **  
5/24/2001  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Page 9 of 25  

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