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C9827JT

更新时间： 2024-02-13 23:00:54
品牌 Logo 应用领域
其他 - ETC 晶体时钟发生器外围集成电路光电二极管
页数 文件大小 规格书
25页 171K
描述
CPU SYSTEM CLOCK GENERATOR|TSSOP|56PIN|PLASTIC

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C9827JT 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP-56针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.25
JESD-30 代码：R-PDSO-G56JESD-609代码：e0
长度：14 mm湿度敏感等级：1
端子数量：56最高工作温度：70 °C
最低工作温度：最大输出时钟频率：200 MHz
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：240
电源：3.3 V主时钟/晶体标称频率：14.318 MHz
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Clock Generators最大压摆率：280 mA
最大供电电压：3.465 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：6.1 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

C9827JT 数据手册

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C9827J  
High Performance Pentium® 4 Clock Synthesizer  
Serial Control Registers (Cont.)  
Byte 0: CPU Clock Register  
Bit  
@Pup  
Pin#  
Description  
7
0
-
Spread Spectrum Enable  
0 = Spread Off, 1 = Spread On  
This is a Read and Write control bit.  
6
5
0
0
-
35  
S1/S3 Mode Select. 0=S1(default) 1=S3 (see note A)  
3V66_1/VCH frequency Select  
0 = 66M selected, 1 = 48M selected  
This is a Read and Write control bit.  
4
3
Pin 53  
Pin 34  
44,45,48,49,51,52  
10,11,12,13,16,17,18  
CPU_STP#. Reflects the current value of the external CPU_STP# (pin 53) This bit is Read Only.  
Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP# is a  
logical AND function of the internal SMBus register bit and the external PCI_STP# pin.  
Frequency Select Bit 2. Reflects the value of SEL2 (pin 40). This bit is Read Only.  
Frequency Select Bit 1. Reflects the value of SEL1 (pin 55). This bit is Read Only.  
Frequency Select Bit 0. Reflects the value of SEL0 (pin 54). This bit is Read Only.  
2
1
0
Pin 40  
Pin 55  
Pin 54  
-
-
-
Note A: When this bit is asserted high “1”, All CPU clocks (TRUE & COMPLEMENT) will be disabled in Hi-Z, to be pulled low externally through the  
pull down resistors, RLA or RLB in fig. 1. This is only applicable when PD# is low. It is not applicable to CPU_STP#  
Byte 1: CPU Clock Register  
Bit  
7
6
@Pup  
Pin 43  
0
0
Pin#  
-
-
Description  
MULT0 (Pin 43) Value. This bit is Read Only.  
Reserved  
Controls CPU2 functionality when CPU_STP# is asserted LOW  
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW  
This is a Read and Write control bit.  
5
44,45  
4
3
0
0
48,49  
51,52  
Controls CPU1 functionality when CPU_STP# is asserted LOW  
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW  
This is a Read and Write control bit.  
Controls CPU0 functionality when CPU_STP# is asserted LOW  
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW  
This is a Read and Write control bit.  
2
1
0
1
1
1
44,45  
48,49  
51,52  
CPU2 Output Control, 1 = enabled, 0 = disable HIGH and CPU/2 disables LOW  
This is a Read and Write control bit.  
CPU1 Output Control, 1 = enabled, 0 = disable HIGH and CPU/1 disables LOW  
This is a Read and Write control bit.  
CPU0 Output Control, 1 = enabled, 0 = disable HIGH and CPU/0 disables LOW  
This is a Read and Write control bit.  
Byte 2: PCI Clock Control Register  
(all bits are read and write functional)  
Byte 3: PCI_F Clock and 48M Control Register  
(all bits are read and write functional)  
Bit  
7
6
@Pup  
0
1
Pin#  
-
18  
Description  
Reserved  
PCI6 Output Control  
1 = enabled, 0 = forced LOW  
PCI5 Output Control  
1 = enabled, 0 = forced LOW  
PCI4 Output Control  
1 = enabled, 0 = forced LOW  
PCI3 Output Control  
1 = enabled, 0 = forced LOW  
PCI2 Output Control  
1 = enabled, 0 = forced LOW  
PCI1 Output Control  
1 = enabled, 0 = forced LOW  
PCI0 Output Control  
Bit  
7
@Pup  
1
Pin#  
38  
Description  
48MDOT Output Control  
1 = enabled, 0 = forced LOW  
48MUSB Output Control  
1 = enabled, 0 = forced LOW  
PCI_STP#, control of PCI_F2.  
0 = Free Running, 1 = Stopped when  
PCI_STP# is LOW  
PCI_STP#, control of PCI_F1.  
0 = Free Running, 1 = Stopped when  
PCI_STP# is LOW  
PCI_STP#, control of PCI_F0.  
0 = Free Running, 1 = Stopped when  
PCI_STP# is LOW  
PCI_F2 Output Control  
1=running, 0=forced LOW  
6
5
1
0
39  
7
5
4
3
2
1
0
1
1
1
1
1
1
17  
16  
13  
12  
11  
10  
4
3
0
0
6
5
2
1
0
1
1
1
7
6
5
1 = enabled, 0 = forced LOW  
PCI_F1 Output Control  
1= running, 0=forced LOW  
PCI_F0 Output Control  
1= running, 0=forced LOW  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07107 Rev. **  
5/24/2001  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Page 4 of 25  
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