Datasheet > C9827JT

C9827JT

更新时间： 2024-01-23 09:56:49

品牌	Logo	应用领域
其他 - ETC		晶体时钟发生器外围集成电路光电二极管
页数	文件大小	规格书
25页	171K
描述
CPU SYSTEM CLOCK GENERATOR\|TSSOP\|56PIN\|PLASTIC

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C9827JT 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	TSSOP-56	针数：	56
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.25
JESD-30 代码：	R-PDSO-G56	JESD-609代码：	e0
长度：	14 mm	湿度敏感等级：	1
端子数量：	56	最高工作温度：	70 °C
最低工作温度：		最大输出时钟频率：	200 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP56,.3,20	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	240
电源：	3.3 V	主时钟/晶体标称频率：	14.318 MHz
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	Clock Generators	最大压摆率：	280 mA
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	6.1 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC	Base Number Matches：	1

C9827JT 数据手册

C9827J

High Performance Pentium® 4 Clock Synthesizer

Pin Description (Cont.)

NAME

PWR

I/O

Description

CPU_STP#

VDD

CPU Clock Disable Input. When asserted low, CPU (0:2) clocks are

synchronously disabled in a high state and CPU/(0:2) clocks are

synchronously disabled in a low state.

66IN/3V66_5

VDD

I/O

Input connection for 66CLK(0:2) output clock buffers if S2 = 1, or output

clock for fixed 66 MHz clock if S2=0. See table on page 1

3.3 volt clock outputs. These clocks are buffered copies of the 66IN clock

or fixed at 66 MHz. See table on page 1

21, 22, 23

66B(0:2)/

3V66(2:4)

VDD

1, 8, 14, 19,

32, 37, 46, 50

4, 9, 15, 20,

27, 31, 36, 47

PWR 3.3V Power Supply

VSS

PWR Common Ground

VSSIREF

PWR Current reference programming input for CPU buffers. A resistor is

connected between this pin and IREF. See CPU Clock current Select

Table in page 18 of this data sheet. This pin should also be returned to

device VSS.

VDDA

PWR Analog power input. Used for PLL and internal analog circuits. Is also

specifically used to detect and determine when power is at an acceptable

level to enable the device to operate.

PU = Internal Pull-Up. PD = Internal Pull-Down. T = Tri level logic input with valid logic voltages of LOW=<0.8V, T=1.0-1.8V and

HIGH=>2.0V

Note: The Pin# column lists the relevant pin number where applicable. The @Pup column gives the default state at

power up.

2-Wire SMBus Control Interface

The 2-wire control interface implements a read/write slave only interface according to SMBus specification. (See IMI

Application Note AN-0022).

The device will accept data written to the D2 address and data may read back from address D3. It will not respond to

any other addresses, and previously set control registers are retained as long as power in maintained on the device.

Serial Control Registers

Following the acknowledge of the Address Byte, two additional bytes must be sent:

1) “Command Code “ byte, and

2) “Byte Count” byte.

Although the data (bits) in the command is considered “don’t care”; it must be sent and will be acknowledged.

After the Command Code and the Byte Count have been acknowledged, the sequence (Byte 0, Byte 1, and Byte 2)

described below will be valid and acknowledged.

Cypress Semiconductor Corporation

525 Los Coches St.

Document#: 38-07107 Rev. **

5/24/2001

Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571

http://www.cypress.com

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