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BU9880GUL-WE2 PDF预览

BU9880GUL-WE2

更新时间： 2024-01-23 09:42:17
品牌 Logo 应用领域
罗姆 - ROHM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
17页 397K
描述
WL-CSP EEPROM family I2C BUS

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中文翻译

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BU9880GUL-WE2 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：ROHS COMPLIANT, WLCSP-8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.51Factory Lead Time：16 weeks
风险等级：1.8最大时钟频率 (fCLK)：0.4 MHz
数据保留时间-最小值：40耐久性：1000000 Write/Erase Cycles
I2C控制字节：1010000RJESD-30 代码：R-PBGA-B8
长度：1.98 mm内存密度：65536 bit
内存集成电路类型：EEPROM内存宽度：8
功能数量：1端子数量：8
字数：8192 words字数代码：8000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：8KX8
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装等效代码：BGA8,3X3,20封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行：SERIAL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.8/5 V
认证状态：Not Qualified座面最大高度：0.55 mm
串行总线类型：I2C最大待机电流：0.000002 A
子类别：EEPROMs最大压摆率：0.002 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：0.5 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：1.58 mm最长写入周期时间 (tWC)：5 ms
写保护：HARDWARE

BU9880GUL-WE2 数据手册

 浏览型号BU9880GUL-WE2的Datasheet PDF文件第7页浏览型号BU9880GUL-WE2的Datasheet PDF文件第8页浏览型号BU9880GUL-WE2的Datasheet PDF文件第9页浏览型号BU9880GUL-WE2的Datasheet PDF文件第11页浏览型号BU9880GUL-WE2的Datasheet PDF文件第12页浏览型号BU9880GUL-WE2的Datasheet PDF文件第13页 
Technical Note  
BU9880GUL-W  
●Read Command  
○Read cycle  
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.  
Random read cycle is a command to read data by designating address, and is used generally.  
Current read cycle is a command to read data of internal address register without designating address, and is used when  
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can  
be read in succession.  
It is necessary to input 'H'  
to the last ACK.  
S
T
A
R
T
W
R
I
T
E
S
T
A
R
T
R
E
A
D
S
T
O
P
SLAVE  
ADDRESS  
1st WORD  
ADDRESS(n)  
2nd WORD  
ADDRESS(n)  
SLAVE  
ADDRESS  
DATA(n)  
SDA  
LINE  
WA  
0
WA  
12  
0
1 0 1 0  
0
0
1 0 1 0  
D7  
D0  
A2  
A1A0  
＊＊  
＊
R A  
A
C
K
A
C
K
R
A
C
A
C
K
/
C
/
W K  
W K  
Fig.36 Random read cycle  
S
T
A
R
T
It is necessary to input 'H'  
to the last ACK.  
R
E
A
D
S
T
O
P
SLAVE  
ADDRESS  
DATA(n)  
SDA  
LINE  
0
1 0 1 0 0  
0
D7  
D0  
A
C
K
R A  
/ C  
W K  
Fig.37 Current read cycle  
S
T
A
R
T
R
E
A
D
S
T
O
P
SLAVE  
ADDRESS  
DATA(n)  
DATA(n+x)  
SDA  
LINE  
0
0
0
1
0
1
0
D7  
D0  
D7  
D0  
R A  
A
C
K
A
C
K
A
C
K
/
C
W K  
Fig.38 Sequential read cycle (in the case of current read cycle)  
・In random read cycle, data of designated word address can be read.  
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential  
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.  
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (µ-COM) side, the next address  
data can be read in succession.  
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H'.  
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.  
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to  
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.  
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL  
signal 'H'.  
www.rohm.com  
© 2010 ROHM Co., Ltd. All rights reserved.  
2010.11 - Rev.A  
10/16  
1...78910111213...17

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